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DSPIC30F2011AT-30E/S Datasheet(PDF) 140 Page - Microchip Technology

Part # DSPIC30F2011AT-30E/S
Description  High-Performance, 16-Bit Digital Signal Controllers
PDF  238 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

DSPIC30F2011AT-30E/S Datasheet(HTML) 140 Page - Microchip Technology

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dsPIC30F6011A/6012A/6013A/6014A
DS70143C-page 138
Preliminary
© 2006 Microchip Technology Inc.
FIGURE 19-3:
CONVERTING 1 CHANNEL AT 200 KSPS, AUTO-SAMPLE START, 1 TAD
SAMPLING TIME
19.8
ADC Acquisition Requirements
The analog input model of the 12-bit ADC is shown in
Figure 19-4. The total sampling time for the ADC is a
function of the internal amplifier settling time and the
holding capacitor charge time.
For the ADC to meet its specified accuracy, the charge
holding capacitor (CHOLD) must be allowed to fully
charge to the voltage level on the analog input pin. The
source impedance (RS), the interconnect impedance
(RIC) and the internal sampling switch (RSS) imped-
ance combine to directly affect the time required to
charge the capacitor CHOLD. The combined impedance
of the analog sources must therefore be small enough
to fully charge the holding capacitor within the chosen
sample time. To minimize the effects of pin leakage
currents on the accuracy of the ADC, the maximum
recommended source impedance, RS, is 2.5 k
Ω. After
the analog input channel is selected (changed), this
sampling function must be completed prior to starting
the conversion. The internal holding capacitor will be in
a discharged state prior to each sample operation.
FIGURE 19-4:
12-BIT ADC ANALOG INPUT MODEL
TCONV
= 14 TAD
TSAMP
= 1 TAD
TSAMP
= 1 TAD
ADCLK
SAMP
DONE
ADCBUF0
ADCBUF1
Instruction Execution BSET ADCON1, ASAM
TCONV
= 14 TAD
CPIN
VA
Rs
ANx
VT = 0.6V
VT = 0.6V
I leakage
RIC
≤ 250Ω
Sampling
Switch
RSS
CHOLD
= DAC capacitance
VSS
VDD
= 18 pF
± 500 nA
Legend: CPIN
VT
I leakage
RIC
RSS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch resistance
= sample/hold capacitance (from DAC)
various junctions
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs
≤ 2.5 kΩ.
RSS
≤ 3 kΩ



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