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LNBH26PQR Datasheet(PDF) 26 Page - STMicroelectronics

Part # LNBH26PQR
Description  Dual LNBS supply and control IC with step-up and I짼C interface
PDF  38 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

LNBH26PQR Datasheet(HTML) 26 Page - STMicroelectronics

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I²C interface protocol
LNBH26
26/38
Doc ID 022771 Rev 1
7.4
Status registers
The STATUS 1, 2 registers can be addressed only in read mode and provide the diagnostic
functions described in the following tables.
N/A = Reserved bit.
All bits reset to 0 at power-on.
Table 11.
STATUS 1 (Read register. Register address = 0X0)
Bit
Name
CH
Value
Description
Bit 0
(LSB)
OLF-A
A
1
VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 9
for the overload operation settings (ISET, PCL, TIMER bits).
0
No overload protection has been triggered to VOUT pin (IOUT < IMAX).
Bit 1
OLF-B
B
1
VOUT pin overload protection has been triggered (IOUT > IMAX). Refer to Table 9
for the overload operation settings (ISET, PCL, TIMER bits).
0
No overload protection has been triggered to VOUT pin (IOUT < IMAX).
Bit 2
VMON-A
A
1
Output voltage (VOUT pin) lower than VMON specification thresholds. Refer to
Table 17.
0
Output voltage (VOUT pin) is within the VMON specifications.
Bit 3
VMON-B
B
1
Output voltage (VOUT pin) lower than VMON specification thresholds. Refer to
Table 17.
0
Output voltage (VOUT pin) is within the VMON specifications.
Bit 4
PDO-A
A
1
Overcurrent detected on output pull-down stage for a time longer than the
deglitch period. This may happen due to an external voltage source present on
the LNB output (VOUT pin).
0
No overcurrent detected on output pull-down stage.
Bit 5
PDO-B
B
1
Overcurrent detected on output pull-down stage for a time longer than the
deglitch period. This may happen due to an external voltage source present on
the LNB output (VOUT pin).
0
No overcurrent detected on output pull-down stage.
Bit 6
OTF
A/B
1
Junction overtemperature is detected, TJ > 150 °C (typ.). See also the THERM
bit setting in
Table 10.
0
Junction overtemperature not detected, TJ <135 °C (typ.). TJ is below thermal
protection threshold.
Bit 7
(MSB)
PNG
A/B
1
Input voltage (VCC pin) lower than LPD minimum thresholds. Refer to Table 13.
0
Input voltage (VCC pin) higher than LPD thresholds. Refer to Table 13.



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