PCF8536AT1 datasheet(15/74 Pages) NXP

15 / 74 page

PCF8536

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Product data sheet

Rev. 2 — 21 February 2012

15 of 74

NXP Semiconductors

PCF8536

Universal LCD low multiplex driver with 6 channel PWM generator

Remark: If an external clock is used, then this clock signal must always be supplied to the

device when the display is on. Removing the clock may freeze the LCD in a DC state

which will damage the LCD material.

8.1.5.2

Timing and frame frequency

The timing of the PCF8536 organizes the internal data flow of the device. This includes

the transfer of display data from the display RAM to the display segment outputs. The

timing also generates the LCD frame frequency which it derives as an integer division of

the clock frequency (see Table 15). The frame frequency is a fixed division of the internal

clock or of the frequency applied to pin OSCCLK when an external clock is used.

[1]

Other values of the frame frequency prescaler see Table 21.

When the internal clock is used, or an external clock with EFR = 1, the LCD frame

frequency can be programmed by software in steps of approximately 10 Hz in the range of

60 Hz to 300 Hz (see Table 21). Furthermore the internal oscillator is factory calibrated,

see Table 44 on page 59.

8.1.6 Command: GPO-output-config

The behavior of the combined LCD and GPO outputs S5/GP5 to S0/GP0 is configured

with the bits described in Table 16.

Each output can be individually configured to be either an LCD segment output, a PWM

output or a static general-purpose output (GPO), see Table 17.

Remark: Even if using GPO only, VLCD must still be applied to the device.

Table 15.

LCD frame frequencies

Frame frequency

Typical external

frequency (Hz)

Nominal frame

frequency (Hz)

EFR bit

Value of q[1]

9600

200

230000

200

fr LCD



clk ext



-----------------

fr LCD



clk ext



48 q



-----------------

Table 16.

GPO-output-config - output mode config command for S5/GP5 to S0/GP0

Bit

Symbol

Value

Description

GPM0 and GPM1

7 to 4

1100

fixed value

3 to 2

GPM1[1:0]

see Table 17

output mode for S1/GP1

1 to 0

GPM0[1:0]

see Table 17

output mode for S0/GP0

GPM2 and GPM3

7 to 4

1101

fixed value

3 to 2

GPM3[1:0]

see Table 17

output mode for S3/GP3

1 to 0

GPM2[1:0]

see Table 17

output mode for S2/GP2

GPM4 and GPM5

7 to 4

1110

fixed value

3 to 2

GPM5[1:0]

see Table 17

output mode for S5/GP5

1 to 0

GPM4[1:0]

see Table 17

output mode for S4/GP4

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