DP83840AVCE datasheet(21/91 Pages) TI1

21 / 91 page

3.0 Functional Description (Continued)

National Semiconductor

Version A

Table II. 4B5B code-group Encoding/Decoding.

*Control code-groups I, J, K, T and R in data fields will be mapped as invalid codes, together with RX_ER asserted.

**Normally, invalid codes (V) are mapped to 6h on RXD[3:0] with RX_ER asserted. If the CODE_ERR bit in the LBREMR (bit 4, register address 18h) is

set, the invalid codes are mapped to 5h on RXD[3:0] with RX_ER asserted. Refer to section 4.14 for further detail.

Name

PCS 5B Code-group

MII 4B Nibble Code

DATA CODES

11110

0000

01001

0001

10100

0010

10101

0011

01010

0100

01011

0101

01110

0110

01111

0111

10010

1000

10011

1001

10110

1010

10111

1011

11010

1100

11011

1101

11100

1110

11101

1111

IDLE AND CONTROL CODES

00100

Halt code-group - Error code

11111

Inter-Packet Idle - 0000*

11000

First Start of Packet - 0101*

10001

Second Start of Packet - 0101*

01101

First End of Packet - 0000*

00111

Second End of Packet - 0000*

INVALID CODES

00000

0110 or 0101*

00001

0110 or 0101*

00010

0110 or 0101*

00011

0110 or 0101*

00101

0110 or 0101*

00110

0110 or 0101*

01000

0110 or 0101*

01100

0110 or 0101*

10000

0110 or 0101*

11001

0110 or 0101*

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