DP83840AVCE datasheet(13/91 Pages) TI1

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2.0 Pin Description (Continued)

National Semiconductor

Version A

2.7 IEEE 1149.1 INTERFACE

The IEEE 1149.1 Standard Test Access Port and Boundary Scan (sometimes referred to as JTAG) interface signals

allow system level boundary scan to be performed. These pins may be left ﬂoating when JTAG testing is not required.

Signal Name

Type

Pin #

Description

TDO

O, Z

TEST DATA OUTPUT: Serial instruction/test output data for the IEEE 1149.1

scan chain.

If Boundary-Scan is not implemented this pin may be left unconnected (NC).

TDI

TEST DATA INPUT: Serial instruction/test input data for the IEEE 1149.1 scan

chain.

TRST

TEST RESET: An asynchronous low going pulse will reset and initialize the IEEE

1149.1 test circuitry.

If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since

it has an internal pull-up resistor (10 k

Ω).

TCLK

TEST CLOCK: Test clock for the IEEE 1149.1 circuitry.

If Boundary-Scan is not implemented this pin may be left unconnected (NC).

TMS

TEST MODE SELECT: Control input to the IEEE 1149.1 test circuitry.

If Boundary-Scan is not implemented, this pin may be left unconnected (NC) since

it has an internal pull-up resistor (10 k

Ω).

I = TTL/CMOS input

O = TTL/CMOS output

Z = TRI-STATE output

J = IEEE 1149.1 pin

DP83840AVCE Datasheet(PDF) 13 Page - Texas Instruments