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DSPIC33FJ64GP710A Datasheet(PDF) 87 Page - Microchip Technology |
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DSPIC33FJ64GP710A Datasheet(HTML) 87 Page - Microchip Technology |
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87 / 338 page  2009 Microchip Technology Inc. Preliminary DS70593B-page 87 dsPIC33FJXXXGPX06A/X08A/X10A bit 0 POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred REGISTER 6-1: RCON: RESET CONTROL REGISTER(1) (CONTINUED) Note 1: All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. 2: If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. 3: For dsPIC33FJ256GPX06A/X08A/X10A devices, this bit is unimplemented and reads back programmed value. |
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