DSPIC33FJ64GP710A datasheet(91/338 Pages) MICROCHIP

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 2009 Microchip Technology Inc.

Preliminary

DS70593B-page 91

dsPIC33FJXXXGPX06A/X08A/X10A

7.0

INTERRUPT CONTROLLER

The

dsPIC33FJXXXGPX06A/X08A/X10A

interrupt

controller reduces the numerous peripheral interrupt

request signals to a single interrupt request signal to

the dsPIC33FJXXXGPX06A/X08A/X10A CPU. It has

the following features:

• Up to eight processor exceptions and software

traps

• Seven user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• A unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Alternate Interrupt Vector Table (AIVT) for debug

support

• Fixed interrupt entry and return latencies

7.1

Interrupt Vector Table

The Interrupt Vector Table is shown in Figure 7-1. The

IVT resides in program memory, starting at location

000004h. The IVT contains 126 vectors consisting of

eight non-maskable trap vectors plus up to 118 sources

of interrupt. In general, each interrupt source has its

own vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority; this priority is linked to their position in the

vector table. All other things being equal, lower

addresses have a higher natural priority. For example,

the interrupt associated with vector 0 will take priority

over interrupts at any other vector address.

dsPIC33FJXXXGPX06A/X08A/X10A devices imple-

ment up to 67 unique interrupts and five non-maskable

traps. These are summarized in Table 7-1 and

Table 7-2.

7.1.1

ALTERNATE VECTOR TABLE

The Alternate Interrupt Vector Table (AIVT) is located

after the IVT, as shown in Figure 7-1. Access to the

AIVT

provided

the

ALTIVT

control

bit

(INTCON2<15>). If the ALTIVT bit is set, all interrupt

and exception processes use the alternate vectors

instead of the default vectors. The alternate vectors are

organized in the same manner as the default vectors.

The AIVT supports debugging by providing a means to

switch

between

application

and

support

environment without requiring the interrupt vectors to

be reprogrammed. This feature also enables switching

between

applications

for

evaluation

different

software algorithms at run time. If the AIVT is not

needed, the AIVT should be programmed with the

same addresses used in the IVT.

7.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The

dsPIC33FJXXXGPX06A/X08A/X10A

device

clears its registers in response to a Reset, which forces

the PC to zero. The digital signal controller then begins

program execution at location 0x000000. The user

programs a GOTO instruction at the Reset address

which redirects program execution to the appropriate

start-up routine.

Note 1: This data sheet summarizes the features

the

dsPIC33FJXXXGPX06A/X08A/

X10A family of devices. However, it is not

intended to be a comprehensive refer-

ence source. To complement the informa-

tion in this data sheet, refer to Section 6.

“Interrupts”

(DS70184)

the

“dsPIC33F/PIC24H

Family

Reference

Manual”, which is available from the

Microchip web site (www.microchip.com).

2: Some registers

and

associated bits

described in this section may not be avail-

able on all devices. Refer to Section 4.0

“Memory Organization” in this data

sheet for device-specific register and bit

information.

Note:

Any unimplemented or unused vector

locations in the IVT and AIVT should be

programmed with the address of a default

interrupt handler routine that contains a

RESET

instruction.

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