PIC10LF322T-EMCSQTP datasheet(116/210 Pages) MICROCHIP

116 / 210 page

PIC10(L)F320/322

DS41585A-page 116

Preliminary

 2011 Microchip Technology Inc.

19.2

CLCx Interrupts

An interrupt will be generated upon a change in the

output value of the CLCx when the appropriate interrupt

enables are set. A rising edge detector and a falling

edge detector are present in each CLC for this purpose.

TheCLCxIF bit of the associated PIR registers will be

set when either edge detector is triggered and its asso-

ciated enable bit is set. The LCxINTP enables rising

edge interrupts and the LCxINTN bit enables falling

edge interrupts. Both are located in the CLCxCON reg-

ister.

To fully enable the interrupt, set the following bits:

• LCxON bit of the CLCxCON register

• CLCxIE bit of the associated PIE registers

• LCxINTP bit of the CLCxCON register (for a rising

edge detection)

• LCxINTN bit of the CLCxCON register (for a falling

edge detection)

• PEIE and GIE bits of the INTCON register

The CLCxIF bit of the associated PIR registers must be

cleared in software as part of the interrupt service. If

another edge is detected while this flag is being

cleared, the flag will still be set at the end of the

sequence.

19.3

Effects of a Reset

The CLCxCON register is cleared to zero as the result

of a Reset. All other selection and gating values remain

unchanged.

19.4

Operation During Sleep

The selection, gating, and logic functions are not

affected by Sleep. Operation will continue provided that

the source signals are also not affected by Sleep.

PIC10LF322T-EMCSQTP Datasheet(PDF) 116 Page - Microchip Technology