A40MX02 datasheet(39/142 Pages) MICROSEMI

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40MX and 42MX FPGA Families

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Predictable Performance: Tight Delay Distributions

Propagation delay between logic modules depends on the resistive and capacitive loading of the routing

tracks, the interconnect elements, and the module inputs being driven. Propagation delay increases as

the length of routing tracks, the number of interconnect elements, or the number of inputs increases.

From a design perspective, the propagation delay can be statistically correlated or modeled by the fanout

(number of loads) driven by a module. Higher fanout usually requires some paths to have longer routing

tracks.

The MX FPGAs deliver a tight fanout delay distribution, which is achieved in two ways: by decreasing the

delay of the interconnect elements and by decreasing the number of interconnect elements per path.

Microsemi’s patented antifuse offers a very low resistive/capacitive interconnect. The antifuses,

fabricated in 0.45 µm lithography, offer nominal levels of 100

Ω resistance and 7.0 fF capacitance per

antifuse.

MX fanout distribution is also tight due to the low number of antifuses required for each interconnect

path. The proprietary architecture limits the number of antifuses per path to a maximum of four, with

90 percent of interconnects using only two antifuses.

Timing Characteristics

Device timing characteristics fall into three categories: family-dependent, device-dependent, and design-

dependent. The input and output buffer characteristics are common to all MX devices. Internal routing

delays are device-dependent; actual delays are not determined until after place-and-route of the user's

design is complete. Delay values may then be determined by using the Designer software utility or by

performing simulation with post-layout delays.

Critical Nets and Typical Nets

Propagation delays are expressed only for typical nets, which are used for initial design performance

evaluation. Critical net delays can then be applied to the most timing critical paths. Critical nets are

determined by net property assignment in Microsemi's Designer software prior to placement and routing.

Up to 6% of the nets in a design may be designated as critical.

Long Tracks

Some nets in the design use long tracks, which are special routing resources that span multiple rows,

columns, or modules. Long tracks employ three and sometimes four antifuse connections, which

increase capacitance and resistance, resulting in longer net delays for macros connected to long tracks.

Typically, up to 6 percent of nets in a fully utilized device require long tracks. Long tracks add

approximately a 3 ns to a 6 ns delay, which is represented statistically in higher fanout (FO=8) routing

delays in the data sheet specifications section, shown in Table 1-28 on page 1-40.

Timing Derating

MX devices are manufactured with a CMOS process. Therefore, device performance varies according to

temperature, voltage, and process changes. Minimum timing parameters reflect maximum operating

voltage, minimum operating temperature and best-case processing. Maximum timing parameters reflect

minimum operating voltage, maximum operating temperature and worst-case processing.

A40MX02 Datasheet(PDF) 39 Page - Microsemi Corporation

A40MX02 Datasheet(HTML) 39 Page - Microsemi Corporation

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