A40MX02 datasheet(49/142 Pages) MICROSEMI

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40MX and 42MX FPGA Families

Re vi s i on 11

1 - 45

CMOS Output Module Timing4

tDLH

Data-to-Pad HIGH

5.5

6.4

7.2

8.5

11.9

tDHL

Data-to-Pad LOW

4.8

5.5

6.2

7.3

10.2

tENZH

Enable Pad Z to HIGH

4.7

5.5

6.2

7.3

10.2

tENZL

Enable Pad Z to LOW

6.8

7.9

8.9

10.5

14.7

tENHZ

Enable Pad HIGH to Z

11.1

12.8

14.5

17.1

23.9

tENLZ

Enable Pad LOW to Z

8.2

9.5

10.7

12.6

17.7

dTLH

Delta LOW to HIGH

0.05

0.06

0.07

0.10

ns/pF

dTHL

Delta HIGH to LOW

0.03

0.04

0.06

ns/pF

Table 1-29 • A40MX02 Timing Characteristics (Nominal 3.3 V Operation) (continued)

(Worst-Case Commercial Conditions, VCC = 3.0 V, TJ = 70°C)

–3 Speed

–2 Speed

–1 Speed

Std Speed

–F Speed

Parameter / Description

Min.

Max.

Min. Max. Min. Max. Min. Max. Min. Max. Units

Notes:

1. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for

estimating device performance. Post-route timing analysis or simulation is required to determine actual performance.

2. Set-up times assume fanout of 3. Further testing information can be obtained from the Timer utility.

3. The hold time for the DFME1A macro may be greater than 0 ns. Use the Timer tool from the Designer software to check

the hold time for this macro.

4. Delays based on 35 pF loading.

A40MX02 Datasheet(PDF) 49 Page - Microsemi Corporation

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