PIC24HJ128GP310 datasheet(143/286 Pages) MICROCHIP

143 / 286 page

DS70175F-page 141

PIC24HJXXXGPX06/X08/X10

14.0 OUTPUT COMPARE

14.1

Setup for Single Output Pulse

Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OCx pin to the low state and generates a single

output pulse.

To generate a single output pulse, the following steps

are required (these steps assume timer source is

initially turned off but this is not a requirement for the

module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock to

the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output pulse

relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to the

rising edge of the pulse.

4. Write the values computed in steps 2 and 3 above

into the Output Compare register, OCxR, and the

Output Compare Secondary register, OCxRS,

respectively.

5. Set Timer Period register, PRy, to value equal to or

greater than value in OCxRS, the Output Compare

Secondary register.

6. Set the OCM bits to ‘100’ and the OCTSEL

(OCxCON<3>) bit to the desired timer source. The

OCx pin state will now be driven low.

7. Set the TON (TyCON<15>) bit to ‘1’, which enables

the compare time base to count.

8. Upon the first match between TMRy and OCxR, the

OCx pin will be driven high.

9. When the incrementing timer, TMRy, matches the

Output Compare Secondary register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin. No additional pulses are

driven onto the OCx pin and it remains at low. As a

result of the second compare match event, the

OCxIF interrupt flag bit is set, which will result in an

interrupt if it is enabled, by setting the OCxIE bit. For

further information on peripheral interrupts, refer to

Section 6.0 “Interrupt Controller”.

10. To initiate another single pulse output, change the

Timer and Compare register settings, if needed,

and then issue a write to set the OCM bits to ‘100’.

Disabling and re-enabling of the timer, and clear-

ing the TMRy register, are not required but may be

advantageous for defining a pulse from a known

event time boundary.

The output compare module does not have to be dis-

abled after the falling edge of the output pulse. Another

pulse can be initiated by rewriting the value of the

OCxCON register.

14.2

Setup for Continuous Output

Pulse Generation

When the OCM control bits (OCxCON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OCx pin to the low state and generates output

pulses on each and every compare match event.

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume timer source is

initially turned off but this is not a requirement for the

module operation):

1. Determine the instruction clock cycle time. Take

into account the frequency of the external clock to

the timer source (if one is used) and the timer

prescaler settings.

2. Calculate time to the rising edge of the output pulse

relative to the TMRy start value (0000h).

3. Calculate the time to the falling edge of the pulse,

based on the desired pulse width and the time to the

rising edge of the pulse.

4. Write the values computed in step 2 and 3 above

into the Output Compare register, OCxR, and the

Output Compare Secondary register, OCxRS,

respectively.

5. Set Timer Period register, PRy, to value equal to or

greater than value in OCxRS, the Output Compare

Secondary register.

6. Set the OCM bits to ‘101’ and the OCTSEL bit to the

desired timer source. The OCx pin state will now be

driven low.

7. Enable the compare time base by setting the TON

(TyCON<15>) bit to ‘1’.

8. Upon the first match between TMRy and OCxR, the

OCx pin will be driven high.

9. When the compare time base, TMRy, matches the

Output Compare Secondary register, OCxRS, the

second and trailing edge (high-to-low) of the pulse

is driven onto the OCx pin.

10. As a result of the second compare match event, the

OCxIF interrupt flag bit set.

11. When the compare time base and the value in its

respective Timer Period register match, the TMRy

12. Steps 8 through 11 are repeated and a continuous

stream of pulses is generated, indefinitely. The

OCxIF flag is set on each OCxRS-TMRy compare

match event.

Note:

This data sheet summarizes the features

of this group of PIC24HJXXXGPX06/X08/

X10 devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to the “PIC24H Family Reference

Manual”. Refer to the Microchip web site

(www.microchip.com)

for

the

latest

PIC24H

Family

Reference

Manual

sections.

PIC24HJ128GP310 Datasheet(PDF) 143 Page - Microchip Technology

PIC24HJ128GP310 Datasheet(HTML) 143 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL