PIC24HJ128GP310 datasheet(147/286 Pages) MICROCHIP

147 / 286 page

DS70175F-page 145

PIC24HJXXXGPX06/X08/X10

15.0 SERIAL PERIPHERAL

INTERFACE (SPI)

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface useful for communicating with

other peripheral or microcontroller devices. These

peripheral devices may be serial EEPROMs, shift regis-

ters, display drivers, A/D converters, etc. The SPI module

is compatible with SPI and SIOP from Motorola®.

15.1

Operating Function Description

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a status

The serial interface consists of 4 pins: SDIx (serial data

input), SDOx (serial data output), SCKx (shift clock

input or output), and SSx (active low slave select).

In Master mode operation, SCK is a clock output but in

Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift

out bits from the SPIxSR to SDOx pin and simulta-

neously shift in data from SDIx pin. An interrupt is gen-

erated when the transfer is complete and the

corresponding interrupt flag bit (SPI1IF or SPI2IF) is

set. This interrupt can be disabled through an interrupt

enable bit (SPI1IE or SPI2IE).

The receive operation is double-buffered. When a com-

plete byte is received, it is transferred from SPIxSR to

SPIxBUF.

If the receive buffer is full when new data is being trans-

ferred from SPIxSR to SPIxBUF, the module will set the

SPIROV bit indicating an overflow condition. The trans-

fer of the data from SPIxSR to SPIxBUF will not be

completed and the new data will be lost. The module

will not respond to SCL transitions while SPIROV is ‘1’,

effectively disabling the module until SPIxBUF is read

by user software.

Transmit writes are also double-buffered. The user

writes to SPIxBUF. When the master or slave transfer

is completed, the contents of the shift register (SPIxSR)

are moved to the receive buffer. If any transmit data has

been written to the buffer register, the contents of the

transmit buffer are moved to SPIxSR. The received

data is thus placed in SPIxBUF and the transmit data in

SPIxSR is ready for the next transfer.

The module supports a basic framed SPI protocol while

operating in either Master or Slave mode. A total of four

framed SPI configurations are supported.

The SPI serial interface consists of four pins:

• SDIx: Serial Data Input

• SDOx: Serial Data Output

• SCKx: Shift Clock Input or Output

• SSx: Active-Low Slave Select or Frame

Synchronization I/O Pulse

The SPI module can be configured to operate using 2,

3 or 4 pins. In the 3-pin mode, SSx is not used. In the

2-pin mode, both SDOx and SSx are not used.

A block diagram of an SPI module is shown in

Figure 15-1. All PIC24HJXXXGPX06/X08/X10 devices

contain two SPI

modules on a single device.

The SPI module contains an 8-word deep FIFO buffer;

the top of the buffer is denoted as SPIxBUF. If DMA

transfers are enabled, the FIFO buffer must be

disabled by clearing the ENHBUF bit (SPIxCON2<0>).

To set up the SPI module for the Master mode of

operation:

If using interrupts:

a) Clear the SPIxIF bit in the respective IFSn

b) Set the SPIxIE bit in the respective IECn

Write the SPIxIP bits in the respective IPCn

Write the desired settings to the SPIxCON

Clear the SPIROV bit (SPIxSTAT<6>).

Enable SPI operation by setting the SPIEN bit

(SPIxSTAT<15>).

Write the data to be transmitted to the SPIxBUF

soon as data is written to the SPIxBUF register.

Note:

This data sheet summarizes the features

of this group of PIC24HJXXXGPX06/X08/

X10 devices. It is not intended to be a

comprehensive reference source. To com-

plement the information in this data sheet,

refer to the “PIC24H Family Reference

Manual”. Refer to the Microchip web site

(www.microchip.com)

for

the

latest

PIC24H

Family

Reference

Manual

sections.

Note:

In this section, the SPI modules are

referred to together as SPIx, or separately

as SPI1 and SPI2. Special Function Reg-

isters will follow a similar notation. For

example, SPIxCON refers to the control

Note:

Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

Note:

Do not perform read-modify-write opera-

tions (such as bit-oriented instructions) on

the SPIxBUF register.

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