THS8083APZP datasheet(49/63 Pages) TI

49 / 63 page

6−6

6.4.8

Output Formatter/Timing Requirements

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

fclk

Maximum conversion rate

THS8083A

MHz

fclk

Minimum conversion rate

MHz

tsu(OUT)

Setup time

1.6

th(OUT),

th(DHS)

Hold time

With respect to 50% level of rising

edge on DATACLK

tsu(DHS)

Setup time

edge on DATACLK

tPLH(OE)

Propagation (delay) time, low-to-high

See Note 13

9.5

tPHL(OE)

Propagation (delay) time, high-to-low-level output

See Note 13

8.5

DATACLK1 output duty cycle

40%

60%

HS and data pipeline delay

See Note 14

See timing diagrams

NOTES: 13. Output timing—OE timing tPLH(OE) is measured from the VIH(MIN) level of OE to the high-impedance state of the output data. The

digital output load is not higher than 10 pF.

OE timing tPHL(OE) is measured from the VIL(MAX) level of OE to the instant when the output data reaches VOH(min) or VOL(max)

output levels. The digital output load is not higher than 10 pF.

14. Pipeline delay (latency)—The number of clock cycles between conversion initiation on an input sample and the corresponding

output data being made available. Once the data pipeline is full, new valid output data are provided every clock cycle.

6.4.9

PLL

6.4.9.1 Open Loop

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DTO frequency range, f(DTO)

THS8083A

See Note 15

MHz

Instantaneous jitter, t(INS)

260

Short-term jitter, t(JOS)

See Note 15

800 (p−p)

240 (rms)

1250 (p−p)

485 (rms)

Phase Increment

See Note 15

11.25

Monotonic

deg

NOTE 15: PLL characterization:

•

Instantaneous jitter is the pk-pk position variation of the clock rising edge between succeeding periods.

•

Short term jitter in open loop or closed loop is defined as the variation of the clock rising edge within one PLL update period (within

the same video line). This can be visually measured by capturing the clock and displaying it on a digital scope with a persistency of

one video line. Numerically, the time instants of the rising edges, at a defined voltage level, of a number N of clock cycles (N = 800)

are captured at a high sampling rate. The average clock time period is calculated from these time instants. The deviation between

each actual time instant and the ideal, based on the average clock time period, is defined as a statistically distributed jitter value

along one line. This jitter is measured on both DATACLK1 and DTOCLK3 outputs.

THS8083APZP Datasheet(PDF) 49 Page - Texas Instruments

THS8083APZP Datasheet(HTML) 49 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63

Datasheet Download

Link URL