THS8083APZP datasheet(16/63 Pages) TI

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3−3

Alternatively, if an external sync separator is present that generates HS and VS from CS, the separated signals can

be fed to the corresponding inputs on the THS8083A and PFD_FREEZE can be left unused. As long as HS has one

pulse per line, the PLL can lock correctly and the HS frequency monitoring register will return the correct value. VS

is only used by the field/frame frequency monitoring register and this will return the correct value as long as VS has

one pulse per field/frame. Both options are shown in Figure 2−4.

Ext. Logic

PFD_FREEZE

THS8083A

Frame Period

PFD_FREEZE High in VBI on Lines Where CS

Has Multiple Rising/Falling Edges Per Line

Option 1: Using PFD_FREEZE

Sync.

Separator

THS8083A

Option 2: Using HS Derived From CS

PFD_FREEZE

Figure 3−4. Using THS8083A With a Composite Sync

as Note that the slicer only works when no video levels are lower than the blanking level and when the internal clamp

circuit is used. This is normally satisfied for G and Y channels, but not for U and V channels. To prevent unnecessary

toggling of the CS output signal, the CS output is switched off (i.e. HI-Z) automatically when mid-level clamping is

chosen for channel 1 (i.e., CLP1_RG=1 in register <CLP_CTRL>).

The source for the slicer is either Ch1 or the dedicated input CS_IN, as selected by register CS_SEL. It is

recommended to use the dedicated input by ac-coupling the Y/G signal input to both Ch1 and CS_IN (using

independent coupling capacitors). The THS8083A performs independent clamping on both inputs.

NOTE:In this revision-A silicon, PDF_FREEZE keeps the DTO output frequency constant and

disables the phase-frequency detector (PFD) from internally updating its error value at every

active edge of HS (this was not the case in prerevision-A versions). Therefore, when

PFD_FREEZE is asserted, the PLL effectively ignores incoming pulses on the HS terminal.

In this revision-A silicon, users do not need to provide an external dc biasing to the Y/G channel

since now a dedicated input terminal for composite sync slicing is provided. This was not the

case in prerevision-A versions, where the sync could only be extracted from Channel1 and a

clamp diode had to be used to establish an initial clamping level. This method is described in

the following section.

When using the dedicated CS_IN terminal, the G/Y signal should be ac-coupled to this terminal

independently from Ch1, i.e., the G/Y signal is routed via a coupling capacitor to CS_IN and

via a second coupling capacitor to Ch1. This is because the THS8083A imposes an

independent (programmable) clamp level for the sync input.

THS8083APZP Datasheet(PDF) 16 Page - Texas Instruments