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PIC18F4550ESOSQTP Datasheet(PDF) 253 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 253 Page - Microchip Technology |
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253 / 430 page  © 2007 Microchip Technology Inc. Preliminary DS39632D-page 251 PIC18F2455/2550/4455/4550 FIGURE 20-6: EUSART RECEIVE BLOCK DIAGRAM FIGURE 20-7: ASYNCHRONOUS RECEPTION, RXDTP = 0 (RX NOT INVERTED) TABLE 20-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 PIR1 SPPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 SPPIP(1) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 RCSTA SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 53 RCREG EUSART Receive Register 53 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 53 BAUDCON ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN 53 SPBRGH EUSART Baud Rate Generator Register High Byte 53 SPBRG EUSART Baud Rate Generator Register Low Byte 53 Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception. Note 1: Reserved in 28-pin devices; always maintain these bits clear. x64 Baud Rate CLK Baud Rate Generator RX Pin Buffer and Control SPEN Data Recovery CREN OERR FERR RSR Register MSb LSb RX9D RCREG Register FIFO Interrupt RCIF RCIE Data Bus 8 ÷ 64 ÷ 16 or Stop Start (8) 7 1 0 RX9 • • • SPBRG SPBRGH BRG16 or ÷ 4 RXDTP Start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 Stop bit Start bit Start bit bit 7/8 Stop bit RX (pin) Rcv Buffer Reg Rcv Shift Reg Read Rcv Buffer Reg RCREG RCIF (Interrupt Flag) OERR bit CREN Word 1 RCREG Word 2 RCREG Stop bit Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word causing the OERR (Overrun) bit to be set. |
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