PIC18F4550ESOSQTP datasheet(28/430 Pages) MICROCHIP

28 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 26

Preliminary

FIGURE 2-3:

EXTERNAL CLOCK INPUT

OPERATION (HS OSC

CONFIGURATION)

2.2.3

EXTERNAL CLOCK INPUT

The EC, ECIO, ECPLL and ECPIO Oscillator modes

require an external clock source to be connected to the

OSC1 pin. There is no oscillator start-up time required

after a Power-on Reset or after an exit from Sleep

mode.

In the EC and ECPLL Oscillator modes, the oscillator

frequency divided by 4 is available on the OSC2 pin.

This signal may be used for test purposes or to

synchronize other logic. Figure 2-4 shows the pin

connections for the EC Oscillator mode.

FIGURE 2-4:

EXTERNAL CLOCK

INPUT OPERATION

(EC AND ECPLL

CONFIGURATION)

The ECIO and ECPIO Oscillator modes function like the

EC and ECPLL modes, except that the OSC2 pin

becomes an additional general purpose I/O pin. The I/O

pin becomes bit 6 of PORTA (RA6). Figure 2-5 shows

the pin connections for the ECIO Oscillator mode.

FIGURE 2-5:

EXTERNAL CLOCK

INPUT OPERATION

(ECIO AND ECPIO

CONFIGURATION)

The internal postscaler for reducing clock frequency in

XT and HS modes is also available in EC and ECIO

modes.

2.2.4

PLL FREQUENCY MULTIPLIER

PIC18F2455/2550/4255/4550 devices include a Phase

Locked Loop (PLL) circuit. This is provided specifically

for USB applications with lower speed oscillators and

can also be used as a microcontroller clock source.

The PLL is enabled in HSPLL, XTPLL, ECPLL and

ECPIO Oscillator modes. It is designed to produce a

fixed 96 MHz reference clock from a fixed 4 MHz input.

The output can then be divided and used for both the

USB and the microcontroller core clock. Because the

PLL has a fixed frequency input and output, there are

eight prescaling options to match the oscillator input

frequency to the PLL.

There is also a separate postscaler option for deriving

the microcontroller clock from the PLL. This allows the

USB peripheral and microcontroller to use the same

oscillator input and still operate at different clock

speeds. In contrast to the postscaler for XT, HS and EC

modes, the available options are 1/2, 1/3, 1/4 and 1/6

of the PLL output.

The HSPLL, ECPLL and ECPIO modes make use of

the HS mode oscillator for frequencies up to 48 MHz.

The prescaler divides the oscillator input by up to 12 to

produce the 4 MHz drive for the PLL. The XTPLL mode

can only use an input frequency of 4 MHz which drives

the PLL directly.

FIGURE 2-6:

PLL BLOCK DIAGRAM

(HS MODE)

OSC1

OSC2

Open

Clock from

Ext. System

PIC18FXXXX

(HS Mode)

OSC1/CLKI

OSC2/CLKO

FOSC/4

Clock from

Ext. System

PIC18FXXXX

OSC1/CLKI

I/O (OSC2)

RA6

Clock from

Ext. System

PIC18FXXXX

VCO

Loop

Filter

and

Prescaler

OSC2

OSC1

PLL Enable

FIN

FOUT

SYSCLK

Phase

Comparator

HS/EC/ECIO/XT Oscillator Enable

÷24

(from CONFIG1H Register)

Oscillator

PIC18F4550ESOSQTP Datasheet(PDF) 28 Page - Microchip Technology

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