PIC18F4550ESOSQTP datasheet(341/430 Pages) MICROCHIP

341 / 430 page

Preliminary

DS39632D-page 339

PIC18F2455/2550/4455/4550

RETURN

Return from Subroutine

Syntax:

RETURN {s}

Operands:

∈ [0,1]

Operation:

(TOS)

→ PC,

if s = 1

(WS)

→ W,

(STATUSS)

→ STATUS,

(BSRS)

→ BSR,

PCLATU, PCLATH are unchanged

Status Affected:

None

Encoding:

0000

0001

001s

Description:

Return from subroutine. The stack is

popped and the top of the stack (TOS)

is loaded into the program counter. If

‘s’= 1, the contents of the shadow

registers WS, STATUSS and BSRS are

loaded into their corresponding

registers, W, STATUS and BSR. If

‘s’ = 0, no update of these registers

occurs (default).

Words:

Cycles:

Q Cycle Activity:

Decode

operation

Process

Data

Pop PC

from stack

operation

Example:

RETURN

After Instruction:

PC = TOS

RLCF

Rotate Left f through Carry

Syntax:

RLCF

f {,d {,a}}

Operands:

≤ f ≤ 255

∈ [0,1]

Operation:

(f<n>)

→ dest<n + 1>,

(f<7>)

→ C,

(C)

→ dest<0>

Status Affected:

C, N, Z

Encoding:

0011

01da

ffff

Description:

The contents of register ‘f’ are rotated

one bit to the left through the Carry

flag. If ‘d’ is ‘0’, the result is placed in

W. If ‘d’ is ‘1’, the result is stored back

in register ‘f’ (default).

If ‘a’ is ‘0’, the Access Bank is

selected. If ‘a’ is ‘1’, the BSR is used to

select the GPR bank (default).

If ‘a’ is ‘0’ and the extended instruction

set is enabled, this instruction

operates in Indexed Literal Offset

Addressing mode whenever

≤ 95 (5Fh). See Section 26.2.3

“Byte-Oriented and Bit-Oriented

Instructions in Indexed Literal Offset

Mode” for details.

Words:

Cycles:

Q Cycle Activity:

Decode

Read

Process

Data

Write to

destination

Example:

RLCF

REG, 0, 0

Before Instruction

REG

1110 0110

After Instruction

REG

1110 0110

1100 1100

PIC18F4550ESOSQTP Datasheet(PDF) 341 Page - Microchip Technology

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