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PIC18F4550ESOSQTP Datasheet(PDF) 417 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 417 Page - Microchip Technology |
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417 / 430 page  © 2007 Microchip Technology Inc. Preliminary DS39632D-page 415 PIC18F2455/2550/4455/4550 DC Characteristics ........................................................... 372 Power-Down and Supply Current ............................ 364 Supply Voltage ......................................................... 363 DCFSNZ .......................................................................... 327 DECF ............................................................................... 326 DECFSZ ........................................................................... 327 Dedicated ICD/ICSP Port ................................................. 305 Development Support ...................................................... 357 Device Differences ........................................................... 409 Device Overview .................................................................. 7 Features (table) ............................................................ 9 New Core Features ...................................................... 7 Other Special Features ................................................ 8 Device Reset Timers .......................................................... 47 Oscillator Start-up Timer (OST) ................................. 47 PLL Lock Time-out ..................................................... 47 Power-up Timer (PWRT) ........................................... 47 Direct Addressing ............................................................... 73 E Effect on Standard PIC Instructions ................................... 75 Effect on Standard PIC MCU Instructions ........................ 354 Electrical Characteristics .................................................. 361 Enhanced Capture/Compare/PWM (ECCP) .................... 149 Associated Registers ............................................... 162 Capture and Compare Modes .................................. 150 Capture Mode. See Capture (ECCP Module). Outputs and Configuration ....................................... 150 Pin Configurations for ECCP1 ................................. 150 PWM Mode. See PWM (ECCP Module). Standard PWM Mode ............................................... 150 Timer Resources ...................................................... 150 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ................................................ 264 A/D Minimum Charging Time ................................... 264 Calculating the Minimum Required A/D Acquisition Time ....................................... 264 Errata ................................................................................... 5 EUSART Asynchronous Mode ................................................ 247 12-Bit Break Transmit and Receive ................. 253 Associated Registers, Receive ........................ 251 Associated Registers, Transmit ....................... 249 Auto-Wake-up on Sync Break Character ......... 252 Receiver ........................................................... 250 Setting up 9-Bit Mode with Address Detect ........................................ 250 Transmitter ....................................................... 247 Baud Rate Generator Operation in Power-Managed Modes .............. 241 Baud Rate Generator (BRG) .................................... 241 Associated Registers ....................................... 242 Auto-Baud Rate Detect .................................... 245 Baud Rate Error, Calculating ........................... 242 Baud Rates, Asynchronous Modes ................. 243 High Baud Rate Select (BRGH Bit) ................. 241 Sampling .......................................................... 241 Synchronous Master Mode ...................................... 254 Associated Registers, Receive ........................ 256 Associated Registers, Transmit ....................... 255 Reception ......................................................... 256 Transmission ................................................... 254 Synchronous Slave Mode ........................................ 257 Associated Registers, Receive ........................ 258 Associated Registers, Transmit ....................... 257 Reception ........................................................ 258 Transmission ................................................... 257 Extended Instruction Set ................................................. 349 ADDFSR .................................................................. 350 ADDULNK ............................................................... 350 and Using MPLAB IDE Tools .................................. 356 CALLW .................................................................... 351 Considerations for Use ............................................ 354 MOVSF .................................................................... 351 MOVSS .................................................................... 352 PUSHL ..................................................................... 352 SUBFSR .................................................................. 353 SUBULNK ................................................................ 353 Syntax ...................................................................... 349 External Clock Input ........................................................... 26 F Fail-Safe Clock Monitor ........................................... 285, 300 Exiting the Operation ............................................... 300 Interrupts in Power-Managed Modes ...................... 301 POR or Wake-up from Sleep ................................... 301 WDT During Oscillator Failure ................................. 300 Fast Register Stack ........................................................... 60 Firmware Instructions ...................................................... 307 Flash Program Memory ..................................................... 79 Associated Registers ................................................. 87 Control Registers ....................................................... 80 EECON1 and EECON2 ..................................... 80 TABLAT (Table Latch) Register ........................ 82 TBLPTR (Table Pointer) Register ...................... 82 Erase Sequence ........................................................ 84 Erasing ...................................................................... 84 Operation During Code-Protect ................................. 87 Protection Against Spurious Writes ........................... 87 Reading ..................................................................... 83 Table Pointer Boundaries Based on Operation ....................... 82 Table Pointer Boundaries .......................................... 82 Table Reads and Table Writes .................................. 79 Unexpected Termination of Write .............................. 87 Write Sequence ......................................................... 85 Write Verify ................................................................ 87 Writing To .................................................................. 85 FSCM. See Fail-Safe Clock Monitor. G GOTO .............................................................................. 328 H Hardware Multiplier ............................................................ 95 Introduction ................................................................ 95 Operation ................................................................... 95 Performance Comparison .......................................... 95 |
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