PIC18F4550ESOSQTP datasheet(138/430 Pages) MICROCHIP

138 / 430 page

PIC18F2455/2550/4455/4550

DS39632D-page 136

Preliminary

13.2

Timer2 Interrupt

Timer2 also can generate an optional device interrupt.

The Timer2 output signal (TMR2 to PR2 match) pro-

vides the input for the 4-bit output counter/postscaler.

This counter generates the TMR2 match interrupt flag

which is latched in TMR2IF (PIR1<1>). The interrupt is

enabled by setting the TMR2 Match Interrupt Enable

bit, TMR2IE (PIE1<1>).

A range of 16 postscale options (from 1:1 through 1:16

inclusive) can be selected with the postscaler control

bits, T2OUTPS3:T2OUTPS0 (T2CON<6:3>).

13.3

TMR2 Output

The unscaled output of TMR2 is available primarily to

the CCP modules, where it is used as a time base for

operations in PWM mode.

Timer2 can be optionally used as the shift clock source

for the MSSP module operating in SPI mode.

Additional information is provided in Section 19.0

“Master Synchronous Serial Port (MSSP) Module”.

FIGURE 13-1:

TIMER2 BLOCK DIAGRAM

TABLE 13-1:

REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Comparator

TMR2 Output

TMR2

Postscaler

Prescaler

PR2

FOSC/4

1:1 to 1:16

1:1, 1:4, 1:16

T2OUTPS3:T2OUTPS0

T2CKPS1:T2CKPS0

Set TMR2IF

Internal Data Bus

Reset

TMR2/PR2

(to PWM or MSSP)

Match

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset

Values

on page

INTCON GIE/GIEH

PEIE/GIEL

TMR0IE

INT0IE

RBIE

TMR0IF

INT0IF

RBIF

PIR1

SPPIF(1)

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

PIE1

SPPIE(1)

ADIE

RCIE

TXIE

SSPIE

CCP1IE

TMR2IE

TMR1IE

IPR1

SPPIP(1)

ADIP

RCIP

TXIP

SSPIP

CCP1IP

TMR2IP

TMR1IP

TMR2

Timer2 Register

T2CON

—

T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON

T2CKPS1 T2CKPS0

PR2

Timer2 Period Register

Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module.

Note 1:

These bits are unimplemented on 28-pin devices; always maintain these bits clear.

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