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PIC18F4550ESOSQTP Datasheet(PDF) 150 Page - Microchip Technology |
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PIC18F4550ESOSQTP Datasheet(HTML) 150 Page - Microchip Technology |
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150 / 430 page  PIC18F2455/2550/4455/4550 DS39632D-page 148 Preliminary © 2007 Microchip Technology Inc. TABLE 15-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 51 RCON IPEN SBOREN(1) — RI TO PD POR BOR 52 PIR1 SPPIF(2) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 54 PIE1 SPPIE(2) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 54 IPR1 SPPIP(2) ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 54 TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 54 TRISC TRISC7 TRISC6 — — — TRISC2 TRISC1 TRISC0 54 TMR2 Timer2 Register 52 PR2 Timer2 Period Register 52 T2CON — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR2ON T2CKPS1 T2CKPS0 52 CCPR1L Capture/Compare/PWM Register 1 Low Byte 53 CCPR1H Capture/Compare/PWM Register 1 High Byte 53 CCP1CON P1M1(2) P1M0(2) DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 53 CCPR2L Capture/Compare/PWM Register 2 Low Byte 53 CCPR2H Capture/Compare/PWM Register 2 High Byte 53 CCP2CON — — DC2B1 DC2B0 CCP2M3 CCP2M2 CCP2M1 CCP2M0 53 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1(2) PSSBD0(2) 53 ECCP1DEL PRSEN PDC6(2) PDC5(2) PDC4(2) PDC3(2) PDC2(2) PDC1(2) PDC0(2) 53 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2. Note 1: The SBOREN bit is only available when BOREN<1:0> = 01; otherwise, the bit reads as ‘0’. 2: These bits are unimplemented on 28-pin devices; always maintain these bits clear. |
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