JS28F640P33TF70 datasheet(43/88 Pages) NUMONYX

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Datasheet

Jul 2011

Order Number:208034-04

P33-65nm SBC

12.0

Power and Reset Specifications

12.1

Power-Up and Power-Down

Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise

VCC and VCCQ should attain their minimum operating voltage before applying VPP.

Power supply transitions should only occur when RST# is low. This protects the device

from accidental programming or erasure during power transitions.

12.2

Reset Specifications

Asserting RST# during a system reset is important with automated program/erase

devices because systems typically expect to read from flash memory when coming out

of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization

may not occur. This is because the flash memory may be providing status information,

instead of array data as expected. Connect RST# to the same active low reset signal

used for CPU initialization.

Also, because the device is disabled when RST# is asserted, it ignores its control inputs

during power-up/down. Invalid bus conditions are masked, providing a level of memory

protection.

Table 17: Power and Reset

Num

Symbol

Parameter

Min

Max

Unit

Notes

tPLPH

RST# pulse width low

100

1,2,3,4

tPLRH

RST# low to device reset during erase

µs

1,3,4,7

RST# low to device reset during program

1,3,4,7

tVCCPH

VCC Power valid to RST# de-assertion (high)

1,4,5,6

Notes:

These specifications are valid for all device versions (packages and speeds).

The device may reset if tPLPH is < tPLPH Min, but this is not guaranteed.

Not applicable if RST# is tied to VCC.

Sampled, but not 100% tested.

When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.

When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.

Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.

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