DSPIC33FJ64GP706 datasheet(312/322 Pages) MICROCHIP

312 / 322 page

dsPIC33FJXXXGPX06/X08/X10

DS70286C-page 310

Revision C (March 2009)

This revision includes minor typographical and

formatting changes throughout the data sheet text.

Global changes include:

• Changed all instances of OSCI to OSC1 and

OSCO to OSC2

• Changed all instances of VDDCORE and

VDDCORE/VCAP to VCAP/VDDCORE

The other changes are referenced by their respective

section in the following table.

TABLE A-2:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-Bit Digital

Signal Controllers”

Updated all pin diagrams to denote the pin voltage tolerance (see “Pin

Diagrams”).

Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which

references pin connections to VSS.

Section 1.0 “Device Overview”

Updated AVDD in the PINOUT I/O Descriptions (see Table 1-1).

Section 2.0 “Guidelines for Getting

Started with 16-Bit Digital Signal

Controllers”

Added new section to the data sheet that provides guidelines on getting

started with 16-bit Digital Signal Controllers.

Section 4.0 “Memory Organization”

Add Accumulator A and B SFRs (ACCAL, ACCAH, ACCAU, ACCBL,

ACCBH and ACCBU) and updated the Reset value for CORCON in the

CPU Core Register Map (see Table 4-1).

Updated Reset values for IPC3, IPC4, IPC11 and IPC13-IPC15 in the

Interrupt Controller Register Map (see Table 4-5).

Updated the Reset value for CLKDIV in the System Control Register Map

(see Table 4-32).

Section 5.0 “Flash Program Memory” Updated Section 5.3 “Programming Operations” with programming

time formula.

Section 9.0 “Oscillator Configuration” Added Note 2 to the Oscillator System Diagram (see Figure 9-1).

Updated default bit values for DOZE<2:0> and FRCDIV<2:0> in the Clock

Divisor (CLKDIV) Register (see Register 9-2).

Added a paragraph regarding FRC accuracy at the end of Section 9.1.1

“System Clock sources”.

Added Note 1 to the FRC Oscillator Tuning (OSCTUN) Register (see

Section 10.0 “Power-Saving

Features”

Added the following registers:

• PMD1: Peripheral Module Disable Control Register 1 (Register 10-1)

• PMD2: Peripheral Module Disable Control Register 2 (Register 10-2)

• PMD3: Peripheral Module Disable Control Register 3 (Register 10-3)

Section 11.0 “I/O Ports”

Added reference to pin diagrams for I/O pin availability and functionality

(see Section 11.2 “Open-Drain Configuration”).

Section 16.0 “Serial Peripheral

Interface (SPI)”

Added Note 2 to the SPIxCON1 register (see Register 16-2).

Section 18.0 “Universal

Asynchronous Receiver Transmitter

(UART)”

Updated the UTXINV bit settings in the UxSTA register (see

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