DSPIC33FJ64GP706 datasheet(310/322 Pages) MICROCHIP

310 / 322 page

dsPIC33FJXXXGPX06/X08/X10

DS70286C-page 308

Section 8.0 “Oscillator Configuration”

Updated the third clock source item (External Clock) in

Section 8.1.1 “System Clock sources”.

Added the center frequency in the OSCTUN register for the FRC

Tuning bits (TUN<5:0>) value 011111 and updated the center

frequency for bits value 011110 (Register 8-4).

Section 15.0 “Serial Peripheral Interface

(SPI)”

Removed redundant information, which is now available in the

related section in the dsPIC33F Family Reference Manual, while

retaining the SPI Module Block Diagram (Figure 15-1).

Section 16.0 “Inter-Integrated Circuit™

(I2C™)”

Removed sections 16.3 through 16.13, while retaining the I2C Block

Diagram (Figure 16-1) (redundant information, which is now

available in the related section in the dsPIC33F Family Reference

Manual).

Section 17.0 “Universal Asynchronous

Receiver Transmitter (UART)”

Removed sections 17.1 through 17.7 (redundant information, which

is now available in the related section in the dsPIC33F Family

Reference Manual).

Section 18.0 “Enhanced CAN (ECAN™)

Module”

Removed sections 18.4 through 18.6 (redundant information, which

is now available in the related section in the dsPIC33F Family

Reference Manual).

Updated Baud Rate Prescaler (BRP<5:0>) bit values in the CiCFG1

Changed default bit value from ‘0’ to ‘1’ for bits 6 through 15

(FLTEN6-FLTEN15) in the CiFEN1 register (Register 18-11).

Section 19.0 “Data Converter Interface

(DCI) Module”

Removed sections 19.3 through 19.7 (redundant information, which

is now available in the related section in the dsPIC33F Family

Reference Manual).

Section 20.0 “10-Bit/12-Bit

Analog-to-Digital Converter (ADC)”

Removed Equation 20-1 (ADC Conversion Clock Period) and Figure

20-3 (ADC Transfer Function (10-Bit Example).

Updated AN14 and AN15 ADC values in the ADC2 Module Block

Diagram (FIGURE 20-2: “ADC2 Module Block Diagram(1)”).

Added Note 2 to ADC Conversion Clock Period Block Diagram

(Figure 20-3).

Updated ADC Conversion Clock Select bits in the ADxCON3

bits have also been updated throughout this data sheet

(Register 20-3).

Added Note to ADxCHS0 register (Register 21-6).

Section 21.0 “Special Features”

Updated address 0xF8000E in the Device Configuration Register

Map (Table 21-1).

Added FICD register content (BKBUG, COE, JTAGEN and

ICS<1:0>) to the dsPIC33F Configuration Bits Description and

removed the last two rows (Table 21-2).

Added a Note after the second paragraph in Section 21.2 “On-Chip

Voltage Regulator”.

TABLE A-1:

MAJOR SECTION UPDATES (CONTINUED)

Section Name

Update Description

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