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PIC16F84A Datasheet(PDF) 325 Page - Microchip Technology |
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PIC16F84A Datasheet(HTML) 325 Page - Microchip Technology |
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325 / 337 page ![]() © 1997 Microchip Technology Inc. DS30234D-page 325 PIC16C6X TMR0 .................................................... 24, 26, 28, 30, 32, 34 TMR0 Clock Source Select bit, T0CS ................................. 36 TMR0 Interrupt .................................................................... 65 TMR0 Overflow Interrupt Enable bit, T0IE .......................... 37 TMR0 Overflow Interrupt Flag bit, T0IF .............................. 37 TMR0 Prescale Selection Table ......................................... 36 TMR0 Source Edge Select bit, T0SE.................................. 36 TMR1 Overflow Interrupt Enable bit, TMR1IE .................... 38 TMR1 Overflow Interrupt Flag bit, TMR1IF ......................... 41 TMR1CS ............................................................................. 71 TMR1H.................................................. 24, 26, 28, 30, 32, 34 TMR1IE ............................................................................... 38 TMR1IF ............................................................................... 41 TMR1L .................................................. 24, 26, 28, 30, 32, 34 TMR1ON ............................................................................. 71 TMR2 .................................................... 24, 26, 28, 30, 32, 34 TMR2 Register .................................................................... 75 TMR2 to PR2 Match Interrupt Enable bit, TMR2IE ............. 38 TMR2 to PR2 Match Interrupt Flag bit, TMR2IF ................. 41 TMR2IE ............................................................................... 38 TMR2IF ............................................................................... 41 TMR2ON ............................................................................. 75 TO ............................................................................... 35, 131 TOUTPS3:TOUTPS0 .......................................................... 75 Transmit Enable bit, TXEN ............................................... 105 Transmit Shift Register Status bit, TRMT ......................... 105 Transmit Status and Control Register ............................... 105 TRISA ............................................. 25, 27, 29, 31, 33, 34, 51 TRISB ............................................. 25, 27, 29, 31, 33, 34, 53 TRISC ....................................... 25, 27, 29, 31, 33, 34, 55, 94 TRISD ............................................. 25, 27, 29, 31, 33, 34, 57 TRISE ............................................. 25, 27, 29, 31, 33, 34, 58 TRMT ................................................................................ 105 TX9 ................................................................................... 105 TX9D ................................................................................. 105 TXEN ................................................................................ 105 TXIE .................................................................................... 39 TXIF .................................................................................... 42 TXREG.................................................. 24, 26, 28, 30, 32, 34 TXSTA .......................................... 25, 27, 29, 31, 33, 34, 105 U UA ................................................................................. 84, 89 Universal Synchronous Asynchronous Receiver Transmitter (USART) Asynchronous Mode Setting Up Transmission................................... 113 Timing Diagram, Master Transmission ............. 113 Transmitter........................................................ 112 Asynchronous Receiver Setting Up Reception ........................................ 115 Timing Diagram ................................................ 114 Asynchronous Receiver Mode Block Diagram .................................................. 114 Section .............................................................. 114 Section ...................................................................... 105 Synchronous Master Mode Reception.......................................................... 118 Section .............................................................. 116 Setting Up Reception ........................................ 118 Setting Up Transmission................................... 116 Timing Diagram, Reception .............................. 119 Timing Diagram, Transmission ......................... 117 Transmission .................................................... 116 Synchronous Slave Mode Reception ..........................................................120 Section ..............................................................120 Setting Up Reception ........................................120 Setting Up Transmission ...................................120 Transmit ............................................................120 Transmit Block Diagram ............................................112 Update Address bit, UA .................................................84, 89 USART Receive Interrupt Enable bit, RCIE ........................39 USART Receive Interrupt Flag bit, RCIF .............................42 USART Transmit Interrupt Enable bit, TXIE ........................39 USART Transmit Interrupt Flag bit, TXIF ............................42 UV Erasable Devices.............................................................7 W Wake-up from Sleep ..........................................................141 Wake-up on Key Depression ...............................................53 Wake-up Using Interrupts ..................................................141 Watchdog Timer (WDT) Block Diagram ...........................................................140 Period ........................................................................140 Programming Considerations ....................................140 Section.......................................................................140 WCOL ............................................................................85, 90 Weak Internal Pull-ups ........................................................53 Write Collision Detect bit, WCOL...................................85, 90 X XMIT_MODE .....................................................................104 XT ......................................................................................130 Z Z ..........................................................................................35 Zero bit ............................................................................9, 35 |
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