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PIC16F84A Datasheet(PDF) 326 Page - Microchip Technology |
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PIC16F84A Datasheet(HTML) 326 Page - Microchip Technology |
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326 / 337 page ![]() PIC16C6X DS30234D-page 326 © 1997 Microchip Technology Inc. LIST OF EQUATION AND EXAMPLES Example 3-1: Instruction Pipeline Flow ............................. 18 Example 4-1: Call of a Subroutine in Page 1 from Page 0 ................................................ 49 Example 4-2: Indirect Addressing ..................................... 49 Example 5-1: Initializing PORTA....................................... 51 Example 5-2: Initializing PORTB....................................... 53 Example 5-3: Initializing PORTC ...................................... 55 Example 5-4: Read-Modify-Write Instructions on an I/O Port ....................................................... 60 Example 7-1: Changing Prescaler (Timer0 →WDT).......... 69 Example 7-2: Changing Prescaler (WDT →Timer0).......... 69 Example 8-1: Reading a 16-bit Free-running Timer ..................................... 73 Example 10-1: Changing Between Capture Prescalers ..................................... 79 Example 10-2: PWM Period and Duty Cycle Calculation ........................................ 81 Example 11-1: Loading the SSPBUF (SSPSR) Register ....................................... 86 Example 11-2: Loading the SSPBUF (SSPSR) Register (PIC16C66/67) .............. 91 Example 12-1: Calculating Baud Rate Error ..................... 107 Example 13-1: Saving Status and W Registers in RAM ...................................... 139 Example 13-2: Saving Status, W, and PCLATH Registers in RAM (All other PIC16C6X devices) ................... 139 LIST OF FIGURES Figure 3-1: PIC16C61 Block Diagram ........................... 10 Figure 3-2: PIC16C62/62A/R62/64/64A/R64 Block Diagram ............................................ 11 Figure 3-3: PIC16C63/R63/65/65A/R65 Block Diagram ............................................ 12 Figure 3-4: PIC16C66/67 Block Diagram ...................... 13 Figure 3-5: Clock/Instruction Cycle ............................... 18 Figure 4-1: PIC16C61 Program Memory Map and Stack .................................................... 19 Figure 4-2: PIC16C62/62A/R62/64/64A/ R64 Program Memory Map and Stack ....... 19 Figure 4-3: PIC16C63/R63/65/65A/R65 Program Memory Map and Stack .............................. 19 Figure 4-4: PIC16C66/67 Program Memory Map and Stack ............................................ 20 Figure 4-5: PIC16C61 Register File Map ...................... 20 Figure 4-6: PIC16C62/62A/R62/64/64A/ R64 Register File Map ................................ 21 Figure 4-7: PIC16C63/R63/65/65A/R65 Register File Map........................................ 21 Figure 4-8: PIC16C66/67 Data Memory Map................ 22 Figure 4-9: STATUS Register (Address 03h, 83h, 103h, 183h) ................. 35 Figure 4-10: OPTION Register (Address 81h, 181h) ................................... 36 Figure 4-11: INTCON Register (Address 0Bh, 8Bh, 10Bh 18Bh)................. 37 Figure 4-12: PIE1 Register for PIC16C62/62A/R62 (Address 8Ch)............................................. 38 Figure 4-13: PIE1 Register for PIC16C63/R63/66 (Address 8Ch)............................................. 39 Figure 4-14: PIE1 Register for PIC16C64/64A/R64 (Address 8Ch)............................................. 39 Figure 4-15: PIE1 Register for PIC16C65/65A/R65/67 (Address 8Ch) ............................................ 40 Figure 4-16: PIR1 Register for PIC16C62/62A/R62 (Address 0Ch) ............................................ 41 Figure 4-17: PIR1 Register for PIC16C63/R63/66 Address 0Ch) ............................................. 42 Figure 4-18: PIR1 Register for PIC16C64/64A/R64 (Address 0Ch) ............................................ 43 Figure 4-19: PIR1 Register for PIC16C65/65A/R65/67 (Address 0Ch) ............................................ 44 Figure 4-20: PIE2 Register (Address 8Dh) ..................... 45 Figure 4-21: PIR2 Register (Address 0Dh) ..................... 46 Figure 4-22: PCON Register for PIC16C62/64/65 (Address 8Eh) ............................................ 47 Figure 4-23: PCON Register for PIC16C62A/R62/63/ R63/64A/R64/65A/R65/66/67 (Address 8Eh) ............................................ 47 Figure 4-24: Loading of PC in Different Situations ......... 48 Figure 4-25: Direct/Indirect Addressing .......................... 49 Figure 5-1: Block Diagram of the RA3:RA0 Pins and the RA5 Pin ................. 51 Figure 5-2: Block Diagram of the RA4/T0CKI Pin......... 51 Figure 5-3: Block Diagram of the RB7:RB4 Pins for PIC16C61/62/64/65....... 53 Figure 5-4: Block Diagram of the RB7:RB4 Pins for PIC16C62A/63/R63/ 64A/65A/R65/66/67 .................................... 54 Figure 5-5: Block Diagram of the RB3:RB0 Pins ............................................ 54 Figure 5-6: PORTC Block Diagram .............................. 55 Figure 5-7: PORTD Block Diagram (In I/O Port Mode)....................................... 57 Figure 5-8: PORTE Block Diagram (In I/O Port Mode)...................................... 58 Figure 5-9: TRISE Register (Address 89h) ................... 58 Figure 5-10: Successive I/O Operation........................... 60 Figure 5-11: PORTD and PORTE as a Parallel Slave Port ................................................... 61 Figure 5-12: Parallel Slave Port Write Waveforms ......... 62 Figure 5-13: Parallel Slave Port Read Waveforms ......... 62 Figure 7-1: Timer0 Block Diagram ................................ 65 Figure 7-2: Timer0 Timing: Internal Clock/No Prescaler .................................................... 65 Figure 7-3: Timer0 Timing: Internal Clock/Prescale 1:2 ..................................... 66 Figure 7-4: TMR0 Interrupt Timing ............................... 66 Figure 7-5: Timer0 Timing With External Clock ............ 67 Figure 7-6: Block Diagram of the Timer0/WDT Prescaler .................................................... 68 Figure 8-1: T1CON: Timer1 Control Register (Address 10h) ............................................. 71 Figure 8-2: Timer1 Block Diagram ................................ 72 Figure 9-1: Timer2 Block Diagram ................................ 75 Figure 9-2: T2CON: Timer2 Control Register (Address 12h) ............................................. 75 Figure 10-1: CCP1CON Register (Address 17h) / CCP2CON Register (Address 1Dh) ........... 78 Figure 10-2: Capture Mode Operation Block Diagram ............................................ 78 Figure 10-3: Compare Mode Operation Block Diagram ............................................ 79 Figure 10-4: Simplified PWM Block Diagram.................. 80 Figure 10-5: PWM Output ............................................... 80 Figure 11-1: SSPSTAT: Sync Serial Port Status Register (Address 94h) .............................. 84 |
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