AS3668_07 datasheet(23/59 Pages) AMSCO

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AS3668

Data Sheet - Detailed Description

Figure 29. Bus Protocol

The bus protocol (as shown in Figure 29) is defined as:

- Data transfer may be initiated only when the bus is not busy.

- During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is

HIGH will be interpreted as control signals.

The bus conditions are defined as:

- Bus Not Busy. Data and clock lines remain HIGH.

- Start Data Transfer. A change in the state of the data line, from HIGH to LOW, while the clock is HIGH, defines a START condition.

- Stop Data Transfer. A change in the state of the data line, from LOW to HIGH, while the clock line is HIGH, defines the STOP condition.

- Data Valid. The state of the data line represents valid data, when, after a START condition, the data line is stable for the duration of the

HIGH period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred

between START and STOP conditions is not limited and is determined by the master device. The information is transferred byte-wise and

each receiver acknowledges with a ninth-bit.

Within the I²C bus specifications a high-speed mode (3.4MHz clock rate) is defined.

- Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The mas-

ter device must generate an extra clock pulse that is associated with this acknowledge bit. A device that acknowledges must pull down the

SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge

clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generat-

ing an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the data line HIGH to

enable the master to generate the STOP condition.

- Figure 29 on page 23 details how data transfer is accomplished on the I²C bus. Depending upon the state of the R/W bit, two types of

data transfer are possible:

- Master Transmitter to Slave Receiver. The first byte transmitted by the master is the slave address, followed by a number of data bytes.

The slave returns an acknowledge bit after the slave address and each received byte.

- Slave Transmitter to Master Receiver. The first byte, the slave address, is transmitted by the master. The slave then returns an acknowl-

edge bit. Next, a number of data bytes are transmitted by the slave to the master. The master returns an acknowledge bit after all received

bytes other than the last byte. At the end of the last received byte, a not-acknowledge is returned. The master device generates all of the

serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or a repeated START condition. Since

a repeated START condition is also the beginning of the next serial transfer, the bus will not be released.

The AS3668 can operate in the following slave modes:

- Slave Receiver Mode. Serial data and clock are received through SDA and SCL. After each byte is received, an acknowledge bit is trans-

mitted. START and STOP conditions are recognized as the beginning and end of a serial transfer. Address recognition is performed by

hardware after reception of the slave address and direction bit.

- Slave Transmitter Mode. The first byte (the slave address) is received and handled as in the slave receiver mode. However, in this mode

the direction bit will indicate that the transfer direction is reversed. Serial data is transmitted on SDA by the AS3668 while the serial clock

is input on SCL. START and STOP conditions are recognized as the beginning and end of a serial transfer.

SDI

SCLK

Slave Address

R/W

Direction Bit

START

3-8

ACK

MSB

Repeat if More Bytes Transferred

STOP or

Repeated

START

ACK from

Receiver

ACK from

Receiver

ACK

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