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AS8525

Datasheet - Application In form atio n

8.4 Wake-Up

When the device enters sleep/standby mode, it can be brought back to the normal mode with the BUS interface. A dominant state on the BUS for

8.5 LIN BUS Transceiver

The AS8525 has an integrated bi-directional bus interface device for data transfer between LIN bus and the LIN protocol controller. The

transceiver consists of a driver with slew rate control, wave shaping and current limitation and a receiver with high voltage comparator followed

by a de-bouncing unit.

8.5.1 Transmit Mode

During transmission the data at the pin TX will be transferred to the BUS driver to generate a bus signal. To minimize the electromagnetic

emission of the bus line, the BUS driver has an integrated slew rate control and wave shaping unit.

Transmitting will be interrupted in the following cases:



Sleep mode



Thermal Shutdown active



Master Reset (VSUP < Vsuvr_on)

The recessive BUS level is generated from the integrated 30k pull up resistor in serial with an active diode This diode prevents the reverse

current of VBUS during differential voltage between VSUP and BUS (VBUS>VSUP). No additional termination resistor is necessary to use the

AS8525 in LIN slave nodes. If this IC is used for LIN master nodes it is necessary that the BUS pin is terminated via an external 1k

Ω resistor in

series with a diode to VBAT.

8.5.2 Receive Mode

The data signals from the BUS pin will be transferred continuously to the pin RX. Short spikes on the bus signal are suppressed by the

implemented debouncing circuit. Including all tolerances the LIN specific receive threshold values of 0.4*VSUP and 0.6*VSUP will be securely

observed.

Table 18. VSUP<Vsuvr_on

Block

Output Signal

TRANSCEIVER=Disabled

LIN=high-z, RX=high-z…

LDO=Disabled

VCC=low

RELAY DRIVER=Disabled

LDRIVE1=high LDRIVE2=high

RESET BLOCK=Disabled

RESET=high-z

RESISTIVE DIVIDER=Disabled

VBAT=high, VBAT_DIV=low