LTC3547

15

3547fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Figure 4c. Transient Response

APPLICATIO S I FOR ATIO

PACKAGE DESCRIPTIO

DDB Package

8-Lead Plastic DFN (3mm × 2mm)

(Reference LTC DWG # 05-08-1702 Rev B)

2.00

±0.10

(2 SIDES)

NOTE:

1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

0.40

± 0.10

BOTTOM VIEW—EXPOSED PAD

0.56

± 0.05

(2 SIDES)

0.75

±0.05

R = 0.115

TYP

R = 0.05

TYP

2.15

±0.05

(2 SIDES)

3.00

±0.10

(2 SIDES)

1

4

8

5

PIN 1 BAR

TOP MARK

(SEE NOTE 6)

0.200 REF

0 – 0.05

(DDB8) DFN 0905 REV B

0.25

± 0.05

2.20

±0.05

(2 SIDES)

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

0.61

±0.05

(2 SIDES)

1.15

±0.05

0.70

±0.05

2.55

±0.05

PACKAGE

OUTLINE

0.25

± 0.05

0.50 BSC

PIN 1

R = 0.20 OR

0.25

× 45°

CHAMFER

0.50 BSC

10

µs/DIV

200mA/DIV

200mA/DIV

COUPLED

100mV/DIV

10

µs/DIV

200mA/DIV

200mA/DIV

COUPLED

100mV/DIV

3547 F04c