LM10QML datasheet(4/28 Pages) NSC

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LM10QML

SNOSAP1A – OCTOBER 2010 – REVISED MARCH 2013

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LM10H Electrical Characteristics DC Parameters

The following conditions apply to all the following parameters, unless otherwise specified.

DC:

At room temperature 1.2V

≤ VS ≤ 45V, VS

-≤ V

CM ≤ V± 0.85V.

DC:

At temperature extremes 1.3V

≤ VS ≤ 45V, VS

-≤ V

CM ≤ V± 1.0V.

Sub-

Symbol

Parameter

Conditions

Notes

Min

Max

Unit

groups

-2.0

2.0

IO = 0mA

-3.0

3.0

2, 3

VS = 1.2V, IO = ±2mA

-3.0

3.0

VIO

Input Offset Voltage

VS = 1.3V, IO = ±2mA

-4.0

4.0

2, 3

VS = 4V, IO = ±20mA

-3.0

3.0

VS = 4V, IO = ±15mA

-4.0

4.0

2, 3

-0.7

0.7

IIO

Input Offset Current

-1.5

1.5

2, 3

IIB

Input Bias Current

2, 3

CMRR

Common Mode Rejection

VS = 45V, -20V ≤ VCM ≤ 24.2V

2, 3

+ = 0.85V,

-0.35V

≥ VS

-≥ -44.2V

+ = 1V,

2, 3

-0.3V

≥ VS

-≥ -44.2V

PSRR

Supply Voltage Rejection

0.85V

≤ VS

+ ≤ 44.6V,

-= -0.35V

≤ VS

+ ≤ 44.6V,

2, 3

-= -0.3V

VRLine

Line Regulation

IRef = 1mA

2, 3

VS = 1.2V, 0 ≤ IO ≤ 1mA

VRLoad

Load Regulation

VS = 1.3V, 0 ≤ IO ≤ 1mA

2, 3

400

µA

Supply Current

500

µA

2, 3

VS = ±20V, IO = 0A,

120

VO = ± 19.95V

5, 6

VS = ±2V, IO = ±20mA,

5.0

VO = ±1.4V

VS = ±2V, IO = ±15mA,

1.5

5, 6

VO = ±1.4V

Large Signal Voltage Gain

+ = 0.85V, V

CM = -0.25V

1.5

-= -0.35V, I

O = ±2mA,

-0.15V

≤ VO ≤ 0.65V,

+ = 1V, V

CM = -0.35V

0.5

5, 6

-= -0.3V, I

O = ±2mA,

+0.05V

≤ VO ≤ 0.65V,

1.1V

≤ VOUT ≤ 6.1V,

See (1)

-5mA

≤ IOUT ≤ -0.1mA

1.2V

≤ VOUT ≤ 6.2V,

See (1)

6.0

5, 6

-5mA

≤ IOUT ≤ -0.1mA

AVSH

Shunt Gain

1.4V

≤ VOUT ≤ 6.4V,

See (1)

8.0

-5mA

≤ IOUT ≤ -0.1mA

1.4V

≤ VOUT ≤ 6.4V,

See (1)

4.0

5, 6

-20mA

≤ IOUT ≤ -0.1mA

(1)

This defines operation in floating applications such as the bootstrapped regulator or two-wire transmitter. Output is connected to the VS

terminal of the IC and input common mode is referred to VS

-(see Typical Applications -). Effect of larger output-voltage swings with

higher load resistance can be accounted for by adding the positive-supply rejection error.

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