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ACSL Datasheet(PDF) 9 Page - AVAGO TECHNOLOGIES LIMITED |
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ACSL Datasheet(HTML) 9 Page - AVAGO TECHNOLOGIES LIMITED |
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9 / 17 page  9 Electrical Specifications Over recommended operating range (3.0V ≤ V DD1 ≤ 3.6V, 3.0V ≤ VDD2 ≤ 3.6V, TA = -40°C to +100°C) unless otherwise specified. All typical specifications are at T A = +25°C , VDD1 = VDD2 = +3.3V. Parameter Symbol Min. Typ. Max. Units Test Conditions Input Threshold Current I TH 2.7 7.0 mA I OL(Sinking)=13 mA, VO= 0.6V High Level Output Current I OH 4.7 100.0 µA I F = 250 µA, VO= 3.3V Low Level Output Voltage V OL 0.36 0.68 V I OL(Sinking)= 13 mA, IF= 7mA High Level Supply Current I DDH 3.2 5.0 mA I F = 0 mA (per channel) Low Level Supply Current I DDL 4.6 7.5 mA I F = 10 mA (per channel) Input Forward Voltage V F 1.25 1.52 1.80 V I F = 10 mA, TA = 25°C Input Reverse Breakdown Voltage BV R 5.0 V I R = 10 µA Input Diode Temperature Coefficient ∆V F / ∆TA -1.8 mV/°C I F = 10 mA Input Capacitance C IN 80 pF f = 1 MHz, V F = 0V Switching Specifications Over recommended operating range (3.0V ≤ V DD1 ≤ 3.6V, 3.0V ≤ VDD2 ≤ 3.6V, IF = 8.0 mA, TA = -40°C to +100°C) unless otherwise specified. All typical specifications are at T A = +25°C , VDD1 = VDD2 = +3.3V. Parameter Symbol Min. Typ. Max. Units Test Conditions Maximum Data Rate 10 15 MBd R L = 350Ω, CL = 15 pF Pulse Width t PW 100 ns R L = 350Ω, CL = 15 pF Propagation Delay Time t PLH 52 100 ns R L = 350Ω, CL = 15 pF to Logic High Output Level[5] Propagation Delay Time t PHL 44 100 ns R L = 350Ω, CL = 15 pF to Logic Low Output Level[6] Pulse Width Distortion |t PHL – tPLH| |PWD| 8 35 ns R L = 350Ω, CL = 15 pF Propagation Delay Skew[7] t PSK 40 ns R L = 350Ω, CL = 15 pF Output Rise Time (10 – 90%) t R 35 ns R L = 350Ω, CL = 15 pF Output Fall Time (10 – 90%) t F 12 ns R L = 350Ω, CL = 15 pF Logic High Common Mode |CM H| 10 kV/µs V cm = 1000V, IF = 0 mA, Transient Immunity [8] V O = 2.0V, RL = 350Ω, T A = 25°C Logic Low Common Mode |CM L| 10 kV/µs V cm = 1000V, IF = 8 mA, Transient Immunity [8] V O = 0.8V, RL = 350Ω, T A = 25°C Notes: 5. t PLH is measured from the 4.0 mA level on the falling edge of the input pulse to the 1.5V level on the rising edge of the output pulse. 6. t PHL is measured from the 4.0 mA level on the rising edge of the input pulse to the 1.5V level on the falling edge of the output pulse. 7. t PSK is equal to the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature and specified test condi- tions. 8. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 2.0V. CML is the maximum common mode voltage slew rate that can be sustained while maintaining V O < 0.8V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. |
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