QT2032PRKCB datasheet(13/220 Pages) AMCC

13 / 220 page

Revision 5.11

AppliedMicro - Confidential & Proprietary

QT2022/32 - Data Sheet: DS3051

Table 3:

QT2022/32 Ball Assignment & Signal Description

Ball

Signal Name

Dir.

Type

Description

CML Outputs

TXOUTP

TXOUTN

CML

9.95 - 10.5Gb/s transmit differential voltage outputs.

100

Ω differential impedance.

D14

D13

RxXAUI0P

RxXAUI0N

CML

3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane

A14

B14

RxXAUI1P

RxXAUI1N

CML

3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane

A12

B12

RxXAUI2P

RxXAUI2N

CML

3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane

A10

B10

RxXAUI3P

RxXAUI3N

CML

3.125 Gb/s differential output data from QT2022/32 to XAUI interface - lane

G13

G14

RXPLLOUTP

RXPLLOUTN

CML

Clock output from receive input data PLL

Used for monitoring only. Leave unconnected.

TXPLLOUTP

TXPLLOUTN

(REFCLK2P,

REFCLK2N)

O/I

CML

Configurable as either a differential transmit clock driver (default) or as a

reference clock input instead of EREFCLK (with MDIO bit 1.C001h.7=1).

The output clock frequency is controlled by MDIObit 1.C001h.2. The default

frequencies are:

With XFP=1: divide-by-64, can be used as reference clock to the XFP

module; 161.13 MHz (10GE) or 164.355 MHz (10GFC)

With XFP=0: divide-by-66; 156.25MHz (10GE) or 159.375 (10GFC)

Enabling the driver circuitry is controlled by MDIO bit 1.C001h.3. By default:

With XFP=1, the driver is enabled

With XFP=0, the driver is disabled

Note: for the case where the pin is configured as a reference clock input, the

driver circuitry is disabled.

VCXOCTLP

VCXOCTLN

CML

QT2032:

Output of phase-frequency detector which drives the external loop filter as

part of the VCXO control.

QT2022:

Unused. Leave unconnected.

CML Inputs

EREFCLKP

EREFCLKN

CML

LAN reference clock input for fiber-side TXPLL.

156.25 MHz (10GE) or 159.375 (10GFC)

On chip 50

Ω terminations to 1.2V. Requires external AC coupling.

SREFCLKP

SREFCLKN

CML

QT2032:

SONET reference clock input for fiber-side TXPLL in WAN-mode

155.52MHz or 622.08MHz selected by REFSEL622 pin;

AC coupled with on chip 50

Ω terminations to 1.2V

QT2022:

Unused. Leave unconnected.

QT2032PRKCB Datasheet(PDF) 13 Page - Applied Micro Circuits Corporation

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