FT313HQ-R datasheet(25/67 Pages) ETC2

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Document No.: FT_000589

FT313H USB2.0 HS Host Controller Datasheet Version 1.2

Clearance No.: FTDI# 318

Bit

Name

Type

Default value

Description

the PORTSC change bits.

USBERR_INT

R/WC

1’b0

USB Error Interrupt

The host controller sets this bit to ‘1’ when the

completion of a USB transaction results in an

error condition.

USB_INT

R/WC

1’b0

USB Interrupt

The host controller sets this bit to ‘1’ upon the

completion of a USB transaction.

Table 5-6 USB status register

5.2.6 USBINTR register (address = 18h)

This register enables and disables reporting of the corresponding interrupt to the software. When a bit is

set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt sources that

are disabled in this register still appear in the USBSTS to allow the software to poll for events.

Bit

Name

Type

Default value

Description

[31:6]

Reserved

26’h0

INT_OAA_EN

R/W

1’b0

Interrupt on Async Advance Enable

When this bit is set to ‘1,’ and the Interrupt on

Async Advance bit in the USBSTS register is

set to ‘1’ also, the host controller will issue an

interrupt at the next interrupt threshold.

H_SYSERR_EN

R/W

1’b0

Host System Error Enable

When this bit is set to ‘1,’ and the Host

System Error Status bit in the USBSTS register

is set to ‘1’ also, the host controller will issue

an interrupt.

FRL_ROL_EN

R/W

1’b0

Frame List Rollover Enable

When this bit is set to ‘1,’ and the Frame List

Rollover bit in the USBSTS register is set to ‘1’

also, the host controller will issue an interrupt.

PO_CHG_DET_EN

R/W

1’b0

Port Change Interrupt Enable

When this bit is set to ‘1,’ and the Port Change

Detect bit in the USBSTS register is set to ‘1’

also, the host controller will issue an interrupt.

USBERR_INT_EN

R/W

1’b0

USB Error Interrupt Enable

When this bit is set to ‘1,’ and the USBERRINT

bit in the USBSTS register is set to ‘1’ also, the

host controller will issue an interrupt at the

next interrupt threshold.

USB_INT_EN

R/W

1’b0

USB Interrupt Enable

When this bit is set to ‘1,’ and the USBINT bit

in the USBSTS register is a set to ‘1’ also, the

host controller will issue an interrupt at the

next interrupt threshold. If set interrupt

threshold to 01h, means that when interrupt

event occurred, the INT signal will be toggled

at once.

Table 5-7 USB interrupt enable register

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