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LM4935RLEVAL Datasheet(PDF) 41 Page - Texas Instruments |
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LM4935RLEVAL Datasheet(HTML) 41 Page - Texas Instruments |
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41 / 91 page  LM4935, LM4935RLEVAL www.ti.com SNAS296D – OCTOBER 2005 – REVISED MARCH 2006 4.2.34 SAR CHANNELS 0 & 1 CONFIGURATION REGISTER This register is used to control channel 0 and 1 of the SAR system. (Note 31) Table 4-33. SAR_SLOT01 (0x1Bh) Bits Field Description 2:0 SLOT_0_FS Programs the sampling frequency of SAR channel 0: SLOT_0_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz 3 SLOT_0_ENB If set then VSAR 1 is sampled into SAR slot 0 which also activates the SAR ADC. 6:4 SLOT_1_FS Programs the sampling frequency of SAR channel 1: SLOT_1_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz 7 SLOT_1_ENB If set then VSAR 2 is sampled into SAR slot 1 which also activates the SAR ADC. 4.2.35 SAR CHANNELS 2 & 3 CONFIGURATION REGISTER This register is used to control channel 2 and 3 of the SAR system. (Note 31) Table 4-34. SAR_SLOT23 (0x1Ch) Bits Field Description 2:0 SLOT_2_FS Programs the sampling frequency of SAR channels 2 and 3: SLOT_2_FS Sample Rate @ 12.000 MHz (point A) 0002 13.888 kHz 0012 3.472 kHz 0102 0.868 kHz 0112 217 Hz 1002 54 Hz 1012 14 Hz 1102 4 Hz 1112 1 Hz 3 SLOT_2_ENB If set then D_VDD / 2 or BB_VDD (depending on SLOT2_VBB) is sampled into SAR slot 2 which also activates the SAR ADC. 4 SLOT_3_ENB If set then A_VDD / 2 is sampled into SAR slot 3 which also activates the SAR ADC. 5 SLOT_2_VBB If set then BB_VDD input is used as input to SAR slot 2 rather than the D_VDD. Copyright © 2005–2006, Texas Instruments Incorporated Application Information 41 Submit Documentation Feedback Product Folder Links: LM4935 LM4935RLEVAL |
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