MB40C348VPFV datasheet(4/19 Pages) FUJITSU

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MB40C348V

(Continued)

Note: The values in parentheses are standard.

Pin No.

Symbol

Description

EXPCLKB

Differential clock (negative-phase) input pin for A/D converter

Fix to “H” level when unused.

PECL level

100

EXPCLK

Differential clock (positive-phase) input pin for A/D converter

Fix to “L” level when unused.

PCLP

Clamp pulse input pin

113

RREF

Internal current setting pin (Add 12 k

Ω for AVss)

103

DSYNC

Delay sync signal output pin

102

DSYNCB

Inverted delay sync signal output pin

CLK

Clock output pin (See “ s TIMING DIAGRAM ”.)

CLKB

ADCLKA

ADCLKB

83 to 90

61 to 68

39 to 46

RDA7 to RDA0

GDA7 to GDA0

BDA7 to BDA0

Digital output pin (Port A)

RDA7, GDA7, BDA7 : MSB

RDA0, GDA0, BDA0 : LSB

71 to 78

51 to 58

29 to 36

RDB7 to RDB0

GDB7 to GDB0

BDB7 to BDB0

Digital output pin (Port B)

RDB7, GDB7, BDB7 : MSB

RDB0, GDB0, BDB0 : LSB

101

COUT

PLL counter output pin

115

LPF

External capacitor / resistor connection pin

117

HHOLD

Phase detector operation is hold by input “H” level

118

HSYNC

Horizontal sync signal input pin

7VREF

Internal voltage output pin (Add 3.3 µF for AVss)

104

Overflow output pin (“H” level output at overflow)

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