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MB40C348VPFV Datasheet(PDF) 5 Page - fujitsu semiconductor |
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MB40C348VPFV Datasheet(HTML) 5 Page - fujitsu semiconductor |
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5 / 19 page  MB40C348V 5 s s s s BLOCK DIAGRAM PCLP RADIN RVIN RVCLP HSYNC HHOLD COUT LPF EXPCLK EXPCLKB EXCLK PVSS PVDD CK CS CLKB CLK DSYNCB DSYNC DVSS AVSS ADCLKB ADCLKA OF BVM GVM RVM VRBM VRB RVRT DVDD AVDD VESD RDB0 ∼ RDB7 RDA0 ∼ RDA7 DATA AMP + CLAMP + A/D × 1.9 A ch B ch 8 bit A/D 8 bit A/D 8 8 8 8 Buffer Buffer Buffer Buffer Buffer Buffer Buffer Buffer 11 bit Shift Reg Counter (12 bit) Filter × 3 ch (1 bit) 2 bit (1 ∼ 1/8) DIV MUX VCO Delay RESET CP PD POL 2 bit (0 ∼ 3 CLK) CLK Delay 1/2 RVRTM PLL Block 6 bit (32 divide, 2CLK) |
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