NG80386SXLP33 datasheet(39/102 Pages) INTEL

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Intel386TM SX MICROPROCESSOR

rupted Restoring null selectors to these registers

before executing the IRET will cause a trap in the

interrupt handler Interrupt routines which expect or

return values in the segment registers will have to

obtainreturn values from the 8086 register images

pushed onto the new stack They will need to know

the mode of the interrupted program in order to

know where to findreturn segment registers and

also to know how to interpret segment register val-

ues

The IRET instruction will perform the inverse of the

above sequence Only the extended IRET instruc-

tion (operand sizee32) can be used and must be

executed at level 0 to change the VM bit to 1

1 If the NT bit in the FLAGS register is on an inter-

task return is performed The current state is

stored in the current TSS and the link field in the

current TSS is used to locate the TSS for the in-

terrupted task which is to be resumed Otherwise

continue with the following sequence

2 Read the FLAGS image from SS8 ESP into the

FLAGS register This will set VM to the value ac-

tive in the interrupted routine

3 Pop off the instruction pointer CSEIP EIP is

popped first then a 32-bit word is popped which

contains the CS value in the lower 16 bits If

VMe0 this CS load is done as a protected mode

segment load If VMe1 this will be done as an

8086 segment load

4 Increment the ESP register by 4 to bypass the

FLAGS image which was ‘popped‘ in step 1

5 If VMe1 load segment registers ES DS FS and

from

memory

locations

SS ESPa8

SS ESPa12

SS ESPa16

and

SS ESPe20

respectively where the new value

of ESP stored in step 4 is used Since VMe1

these are done as 8086 segment register loads

Else if VMe0 check that the selectors in ES DS

FS and GS are valid in the interrupted routine

Null out invalid selectors to trap if an attempt is

made to access through them

6 If RPL(CS)lCPL pop the stack pointer SSESP

from the stack The ESP register is popped first

followed by 32-bits containing SS in the lower 16

bits If VMe0 SS is loaded as a protected mode

segment register load If VMe1 an 8086 seg-

ment register load is used

7 Resume execution of the interrupted routine The

VM bit in the FLAGS register (restored from the

interrupt routine’s stack image in step 1) deter-

mines whether the processor resumes the inter-

rupted routine in Protected mode or Virtual 8086

Mode

50 FUNCTIONAL DATA

The Intel386 SX Microprocessor features a straight-

forward functional interface to the external hard-

ware The Intel386 SX Microprocessor has separate

parallel buses for data and address The data bus is

16-bits in width and bi-directional The address bus

outputs 24-bit address values using 23 address lines

and two byte enable signals

The Intel386 SX Microprocessor has two selectable

address bus cycles address pipelined and non-ad-

dress pipelined The address pipelining option al-

lows as much time as possible for data access by

starting the pending bus cycle before the present

bus cycle is finished A non-pipelined bus cycle

gives the highest bus performance by executing ev-

ery bus cycle in two processor CLK cycles For maxi-

mum design flexibility the address pipelining option

is selectable on a cycle-by-cycle basis

The processor’s bus cycle is the basic mechanism

for information transfer either from system to proc-

essor or from processor to system Intel386 SX Mi-

croprocessor bus cycles perform data transfer in a

minimum of only two clock periods The maximum

transfer bandwidth at 16 MHz is therefore 16

Mbytessec However any bus cycle will be extend-

ed for more than two clock periods if external hard-

ware withholds acknowledgement of the cycle

The Intel386 SX Microprocessor can relinquish con-

trol of its local buses to allow mastership by other

devices such as direct memory access (DMA) chan-

nels When relinquished HLDA is the only output pin

driven by the Intel386 SX Microprocessor providing

near-complete isolation of the processor from its

system (all other output pins are in a float condition)

51 Signal Description Overview

Ahead is a brief description of the Intel386 SX Micro-

processor input and output signals arranged by func-

tional groups Note the

symbol at the end of a

signal name indicates the active or asserted state

occurs when the signal is at a LOW voltage When

is present after the signal name the signal is

asserted when at the HIGH voltage level

Example signal MIO

HIGH voltage indicates

Memory selected

LOW voltage indicates

IO selected

The signal descriptions sometimes refer to AC tim-

ing parameters such as ‘t25 Reset Setup Time‘ and

‘t26 Reset Hold Time‘ The values of these parame-

ters can be found in Table 74

NG80386SXLP33 Datasheet(PDF) 39 Page - Intel Corporation

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