GMS87C1102 datasheet(72/89 Pages) HYNIX

72 / 89 page

GMS81C1102 / GMS81C1202

Jan. 2002 ver 2.0

23. POWER FAIL PROCESSOR

The GMS81C1202 has an on-chip power fail detection cir-

cuitry to immunize against power noise. A configuration

ble (if set) the Power-fail Detect circuitry. If VDD falls be-

low 3.0~4.0V range for longer than 50 nS, the Power fail

situation may reset MCU according to PFDM bit of PFDR.

As below PFDR register is not implemented on the in-cir-

cuit emulator, user can not experiment with it. Therefore,

after final development of user program, this function may

be experimented.

Note: Power fail processor function is not available on 3V

operation, because this function will detect power

fail all the time.

Figure 23-1 Power Fail Detector Register

Figure 23-2 Example S/W of RESET by Power fail

PFDR

ADDRESS : EFH

RESET VALUE : -----100

PFDIS

PFDM

PFS

Reserved

Power Fail Status

0 : Normal Operate

1 : This bit force to "1" when

Operation Mode

0 : System clock freezing during power fail

1 : MCU will be reset during power fail

Disable Flag

0 : Power fail detection enable

1 : Power fail detection disable

Power Fail Detector Register

Power fail was detected

FUNTION

EXECUTION

INITIALIZE RAM DATA

PFS =1

RESET VECTOR

INITIALIZE ALL PORTS

INITIALIZE REGISTERS

RAM CLEAR

YES

Skip the

initial routine

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