HC2509C

March 1999

1

HC2509C

Features

l Phase-Locked Loop Clock Distribution for

Synchronous DRAM Applications

l Supports PC-100 and Meets “PC100 SDRAM

registered DIMM Specification Rev. 1.2”

l Distributes One Clock Input to One Bank of Five

and One Bank of Four Outputs

l No External RC Network Required

l External Feedback (FBIN) Pin is Used to

Synchronize the Outputs to the Clock Input

l Separate Output Enable for Each Output Bank

l 125 MHz Maximum Frequency

l On-chip Series Damping Resistors

l Support Spread Spectrum Clock(SSC)

Synthesizers

l ESD Protection Exceeds 3000 V per MIL-STD-

883, Method 3015 ; Exceeds 350 V Using

Machine

Model ( C = 200 pF, R = 0 )

l Latch-Up Performance Exceeds 400 mA per

JESD 17

l Packaged in Plastic 24-Pin Thin Shrink Small-

Outline Package

Pin Configuration

General Description

The HC2509C is a low-skew, low jitter, phase-locked

loop(PLL) clock driver, distributing high frequency

clock signals for SDRAM.

integrated series-damping resistors that make it ideal

for driving point-to-point loads. The propagation delay

from the CLK input to any clock output is nearly zero.

One bank of five outputs and one bank of four outputs

provide nine low-skew and low-jitter clocks. Each

bank

of

outputs

can

be

enabled

or

disabled

separately via the control inputs (1G and 2G). Output

signal duty cycles are adjusted to 50 percent,

independent of the duty cycle at CLK.

The HC2509C is specially designed to interface with

high speed SDRAM applications in the range of

25MHz to 125MHz and includes an internal RC

network which provides excellent jitter characteristics

and eliminates the needs for external components.

For the test purpose, the PLL can be bypassed by

The HC2509C is characterized for operation from 0

°C

to 85

°C.

Function Table

INPUTS

OUTPUTS

1Y

2Y

1G

2G

CLK

(0:4)

(0:3)

FBOUT

X

X

L

L

L

L

L

L

H

L

L

H

L

H

H

L

H

H

H

L

H

H

L

H

H

H

H

H

H

H

TSSOP 24 PACKAGE

(TOP VIEW)

AGND

Vcc

1Y0

1Y1

1Y2

GND

GND

1Y3

1Y4

Vcc

1G

FBOUT

CLK

AVcc

Vcc

2Y0

2Y1

GND

GND

2Y2

2Y3

Vcc

2G

FBIN

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13