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HMS87C4260 Datasheet(PDF) 89 Page - Hynix Semiconductor |
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HMS87C4260 Datasheet(HTML) 89 Page - Hynix Semiconductor |
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89 / 110 page ![]() HMS81C4x60 November 2001 Ver 1.1 87 Figure 19-4 I2C status Register I2C control register It controls communication data format. It controls SCL mode, SCL frequency, etc. It contains 8bit data to transmit to external device when tr- asmitter mode, or received 8bit data from external device when receive mode. Figure 19-5 I2C control Register Figure 19-6 Interrupt request signal generation timing 0LRB Last received bit. it is used for receive confirmation. If ACK is returned, LRB=0, or not 1. Bit No. Name Function Table 19-1 Bit function ICSR ADDRESS : 00DAH RESET VALUE : 0001 0000b RW RW RW RW R R R R MST TRX BB PIN AL AD0 ADRb LRB ICCR ADDRESS : 00DBH RESET VALUE : 0000 0000b ESO CCR3 CCR2 CCR1 CCR0 BSEL0 RW RW RW RW RW RW RW BSEL1 ACKb RW SCL PIN I2C Request Bit No. Name Function 7 6 BSEL1 BSEL0 I2C connection control. 00: No connection 01: SCL0, SDA0 10: SCL1, SDA1 11: SCL0, SDA0, SCL1, SDA1 5ACK If acknowlege clock is returned, this bit is 0, or not 1. 4 ESO I2C Bus interface use enable flag 0: Disabled 1: Enabled 3 2 1 0 CCR3 CCR2 CCR1 CCR0 SCL Frequency selection SCL frequency = fex / (12 * CCR) Value fex = 4MHz 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Not allowed Not allowed 333.3KHz 222.2KHz 166.6KHz 133.3KHz 111.1KHz 95.2KHz 83.3KHz 74.1KHz 66.6KHz 60.6KHz 55.5KHz 51.3KHz 47.6KHz 44.4KHz Table 19-2 Bit function |
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