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HMS87C4260 Datasheet(PDF) 39 Page - Hynix Semiconductor |
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HMS87C4260 Datasheet(HTML) 39 Page - Hynix Semiconductor |
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39 / 110 page  HMS81C4x60 November 2001 Ver 1.1 37 Peripheral Clock supplied from prescaler can be stopped by ENPCK. Peripheral clock is determined by CKCTLR Register.(However, PS11 cannot be stopped by ENPCK) Figure 10-5 Clock Control Register INITIAL VALUE: --00 0000b ADDRESS: 00F6H MSB LSB B.I.T input clock select B.I.T clear (when write) B.I.T value (when read) WWWWWW WW BTS1 BTS2 BT C L EN PC K WD TO N - -B TS 0 CKCTLR 0 : B.I.T Free-run 1 : B.I.T clear (Auto reset when after 1 cycle) 000 : PS4 (4 µS) 001 : PS5 (8 µS) 010 : PS6 (16 µS) 011 : PS7 (32 µS) 100 : PS8 (64 µS) 101 : PS9 (128 µS) 110 : PS10 (256 µS) 111 : PS11 (512 µS) Peripherial clock enable (when write) 0 : Peripherial clock stop 1 : Peripherial clock supply WDT function control(when write) 0 : 6 bit TIMER 1 : WATCH-DOG TIMER data : 00h ~ FFh |
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