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28F128 Datasheet(PDF) 13 Page - Intel Corporation |
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28F128 Datasheet(HTML) 13 Page - Intel Corporation |
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13 / 58 page ![]() 28F128J3A, 28F640J3A, 28F320J3A Preliminary 7 3.0 Bus Operations The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. NOTE: For single-chip applications, CE2 and CE1 can be strapped to GND. Figure 4. Memory Map Table 2. Chip Enable Truth Table CE2 CE1 CE0 DEVICE VIL VIL VIL Enabled VIL VIL VIH Disabled VIL VIH VIL Disabled VIL VIH VIH Disabled VIH VIL VIL Enabled VIH VIL VIH Enabled VIH VIH VIL Enabled VIH VIH VIH Disabled 64-Kword Block 64-Kword Block 64-Kword Block 64-Kword Block Word Wide (x16) Mode 1FFFFF 1F0000 7FFFFF 7F0000 01FFFF 010000 00FFFF 000000 A [23-1]: 128 Mbit A [22-1]: 64 Mbit A [21-1]: 32 Mbit 128-Kbyte Block 128-Kbyte Block 128-Kbyte Block 128-Kbyte Block Byte-Wide (x8) Mode 3FFFFF 3E0000 FFFFFF FE0000 03FFFF 020000 01FFFF 000000 A [23-0]:128 Mbit A [22-0]: 64 Mbit A [21-0]: 32 Mbit 64-Kword Block 3FFFFF 3F0000 128-Kbyte Block 7FFFFF 7E0000 31 1 0 127 63 31 1 0 127 63 |
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