28F128 datasheet(21/58 Pages) INTEL

21 / 58 page

28F128J3A, 28F640J3A, 28F320J3A

Preliminary

NOTES:

1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a

function of device bus width and mode.

2. BA = Block Address beginning location (i.e., 02000h is block 2’s beginning location when the block size is

128 Kbyte).

3. Offset 15 defines “P” which points to the Primary Intel-Specific Extended Query Table.

4.2.3

Block Status Register

The block status register indicates whether an erase operation completed successfully or whether a

given block is locked or can be accessed for flash program/erase operations.

NOTE:

1. BA = The beginning location of a Block Address (i.e., 008000h is block 1’s (64-KB block) beginning location

in word mode).

4.2.4

CFI Query Identification String

The CFI Query Identification String provides verification that the component supports the

Common Flash Interface specification. It also indicates the specification version and supported

vendor-specified command set(s).

Table 7.

Query Structure(1)

Offset

Sub-Section Name

Description

00h

Manufacturer Code

01h

Device Code

(BA+2)h(2)

Block Status Register

Block-Specific Information

04-0Fh

Reserved

Reserved for Vendor-Specific Information

10h

CFI Query Identification String

Reserved for Vendor-Specific Information

1Bh

System Interface Information

Command Set ID and Vendor Data Offset

27h

Device Geometry Definition

Flash Device Layout

P(3)

Primary Intel-Specific Extended

Query Table

Vendor-Defined Additional Information Specific to the

Primary Vendor Algorithm

Table 8.

Block Status Register

Offset

Length

Description

Address

Value

(BA+2)h(1)

Block Lock Status Register

BA+2:

--00 or --01

BSR.0 Block Lock Status

0 = Unlocked

1 = Locked

BA+2:

(bit 0): 0 or 1

BSR 1–7: Reserved for Future Use

BA+2:

(bit 1–7): 0

Table 9.

CFI Identification

Offset

Length

Description

Add.

Hex

Code

Value

10h

Query-unique ASCII string “QRY”

--51

“Q”

11:

--52

“R”

12:

--59

“Y”

13h

Primary vendor command set and control interface ID code.

13:

--01

16-bit ID code for vendor-specified algorithms

14:

--00

15h

Extended Query Table primary algorithm address

15:

--31

16:

--00

28F128 Datasheet(PDF) 21 Page - Intel Corporation

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