376 datasheet(47/95 Pages) INTEL

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376 EMBEDDED PROCESSOR

240182 – 25

Following any idle bus state (Ti) the bus cycle is always non-pipelined and NA is only sampled during wait states To

start address pipelining after an idle state requires a non-pipelined cycle with at least one wait state (cycle 1 above)

The pipelined cycles (2 3 4 above) are shown with various numbers of wait states

Figure 410 Fastest Transition to Pipelined Bus Cycle Following Idle Bus State

The complete bus state transition diagram including

pipelining is given by Figure 412 Note it is a super-

set of the diagram for non-pipelined only and the

three additional bus states for pipelining are drawn

in bold

The fastest bus cycle with pipelining consists of just

two bus states T1P and T2P (recall for non-pipe-

lined it is T1 and T2) T1P is the first bus state of a

pipelined cycle

Initiating and Maintaining Pipelined Bus Cycles

Using the state diagram Figure 412 observe the

transitions from an idle state Ti to the beginning of

a pipelined bus cycle T1P From an idle state Ti the

first bus cycle must begin with T1 and is therefore a

non-pipelined bus cycle The next bus cycle will be

pipelined however provided NA is asserted and the

first bus cycle ends in a T2P state (the address and

status for the next bus cycle is driven during T2P)

The fastest path from an idle state to a pipelined bus

cycle is shown in bold below

Ti Ti

T1 – T2 – T2P

T1P – T2P

idle

non-pipelined

pipelined

states

cycle

376 Datasheet(PDF) 47 Page - Intel Corporation