82378ZB datasheet(21/137 Pages) INTEL

21 / 137 page

82378ZB (SIO) AND 82379 (SIO.A)

2.8. Interrupt Controller Signals

Signal Name

Type

Description

IRQ[15,14,11:

9, 7:3,1]

INTERRUPT REQUEST: The IRQ signals provide both system board components

and ISA Bus I/O devices with a mechanism for asynchronously interrupting the

CPU. The assertion mode of these inputs (edge or level triggered) is programmable

via the ELCR Register. Upon PCIRST#, the IRQ lines are placed in edge-triggered

mode.

NOTE:

For the 82378ZB, an active IRQ input must remain asserted until after the interrupt is

acknowledged. If the input goes inactive before this time, a DEFAULT IRQ7 occurs when

the CPU acknowledges the interrupt.

For the 82379AB, A low to high transition on IRQ1 is latched by the 82379AB. The latch is

cleared by a read of address 60h.

Refer to the Utility Bus Signal descriptions for IRQ12 and IRQ13 signal descriptions.

IRQ8#

INTERRUPT REQUEST EIGHT SIGNAL: IRQ8# is an active low interrupt input.

The assertion mode of these inputs (edge or level triggered) is programmable via

the ELCR Register. Upon PCIRST#, the IRQ lines are placed in edge-triggered

mode.

NOTE:

For the 82378ZB, IRQ8# must remain asserted until after the interrupt is acknowledged. If

the input goes inactive before this time, a DEFAULT IRQ7 will occur when the CPU

acknowledges the interrupt.

For the 82379AB, this pin requires an external 8.2 K

Ω pull-up resistor.

INT

CPU INTERRUPT: INT is driven by the SIO/SIO.A to signal the CPU that an

interrupt request is pending and needs to be serviced. It is asynchronous with

respect to SYSCLK or PCICLK and is always an output. The interrupt controller

must be programmed following a reset to ensure that INT is at a known state. Upon

PCIRST#, INT is driven low.

NMI

NON-MASKABLE INTERRUPT: NMI is used to force a non-maskable interrupt to

the CPU. The SIO/SIO.A generates an NMI when either SERR# or IOCHK# is

asserted, depending on how the NMI Status and Control Register is programmed.

The CPU detects an NMI when it detects a rising edge on NMI. After the NMI

interrupt routine processes the interrupt, the NMI status bits in the NMI Status and

Control Register are cleared by software. The NMI interrupt routine must read this

corresponding NMI source enable/disable bit in the NMI Status and Control

must be set to 0, and the NMI mask bit in the NMI Enable/Disable and Real-Time

Clock Address Register must be set to 0. Upon PCIRST#, this signal is driven low.

82378ZB Datasheet(PDF) 21 Page - Intel Corporation

82378ZB Datasheet(HTML) 21 Page - Intel Corporation

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