82378ZB datasheet(46/137 Pages) INTEL

46 / 137 page

82378ZB (SIO) AND 82379AB (SIO.A)

Bit

Description

Keyboard Controller Address Location Enable: 1=Enable. 0=Disable. When disabled, the keyboard

controller encoded chip select signals (ECSADDR[2:0]) and the Utility Bus transceiver signal

(UBUSOE#) are not generated for the address locations below.

For the 82378ZB, the enabled address locations are 60h, 62h, 64h, and 66h.

For the 82379AB, the enabled address locations are 60h, and 64h.

RTC Address Location Enable: Enables (1) or disables (0) the RTC address locations 70–77h. When

this bit is set to 0, the RTC encoded chip select signals (ECSADDR[2:0]), RTCALE#, RTCCS#, and

UBUSOE# signals are not generated for these addresses.

3.1.21. UBCSB—UTILITY BUS CHIP SELECT B REGISTER

Address Offset:

4Fh

Default Value:

4Fh

Attribute:

Read/Write

This register is used to enable/disable accesses to the serial ports and parallel port locations supported by the

SIO/SIO.A. When disabled, the ECSADDR(2:0) encoded chip select bits and Utility Bus Transceiver control

signal (UBUSOE#), for that device, are not generated. This register is also used to disable accesses to Port 92

and enable or disable configuration RAM decode.

Bit

Description

Configuration RAM Decode Enable: This bit is used to enable (bit 7=1) or disable (bit 7=0) I/O write

accesses to location 0C00h and I/O read/write accesses to locations 0800–08FFh. When enabled, the

encoded chip select signals for generating an external configuration page chip select (CPAGECS#) are

generated for accesses to 0C00h. The encoded chip select signals for generating an external

configuration memory chip select (CFIGMEMCS#) are generated for accesses to 0800–08FFh. When

bit 7=0, configuration RAM decode is disabled and the CPAGECS# and CFIGMEMCS# are not

generated for the corresponding accesses.

Port 92 Enable: 1=Enable; 0=Disable.

5:4

Parallel Port Enable: These bits are used to select the parallel port address range: (LPT1, LPT2,

LPT3, or disable). When a PCIRST# occurs, this field is set to 00 (LPT1).

Bit[5:4]

Function

Bit[5:4]

Function

3BC–3BFh (LPT1)

278–27Fh (LPT3)

378–37Fh (LPT2)

Disabled

3:2

Serial Port B Enable: These bits are used to assign Serial Port B address range: (COM1, COM2, or

disable). If either COM1 or COM2 address ranges are selected, the encoded chip select signals

[ECSADDR(2:0)] for Port B will be generated. A PCIRST# sets bit[3:2] to 11 (Port B disabled). Note

that, If Serial Port A and B are programmed for the same I/O address, the encoded chip select signals,

ECSADDR(2:0), for Port B are disabled.

Bit[3:2]

Function

Bit[3:2]

Function

3F8–3FFh (COM1)

Reserved

2F8–2FFh (COM2)

Port B Disabled

82378ZB Datasheet(PDF) 46 Page - Intel Corporation

82378ZB Datasheet(HTML) 46 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL