M80C186EB-13 datasheet(13/56 Pages) INTEL

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M80C186EB

The Generic Chip-Selects (GCS70) are multiplexed

with an output only Port function Any channel that is

being used as a chip-select must be disabled as a

port pin by correctly programming the port pin con-

trol registers (see the following section)

IO PORT UNIT

The IO Port Unit (IPU) on the M80C186EB supports

two 8-bit channels of input output or inputoutput

operation Port 1 is multiplexed with the chip select

pins and is output only Most of Port 2 is multiplexed

with the serial channel pins Port 2 pins are limited to

either an output or input function depending on the

operation of the serial pin it is multiplexed with

Two bits of Port 2 are not multiplexed with any other

peripheral functions and can be used as either an

input or an output function A port direction register

is used to define the function of the port pin The

output for these two pins are open drain

Besides a direction register each port channel has a

data latch register port pin register and a port multi-

plexer control register

REFRESH CONTROL UNIT

The Refresh Control Unit (RCU) automatically gen-

erates a periodic memory read bus cycle to keep

dynamic or pseudo-static memory refreshed A 9-bit

counter controls the number of clocks between re-

fresh requests

A 12-bit address generator is maintained by the RCU

and is presented on the A121 address lines during

the refresh bus cycle The address generator is in-

cremented only after the refresh bus cycle is run

This ensures that all address combinations will be

presented to the memory array even if the refresh

bus cycle is not run before another request is gener-

ated Address bits A1913 are programmable to al-

low the refresh address block to be located on any 8

Kbyte boundary

The chip-select unit is active during refresh bus cy-

cles This means that a chip-select will go active if

the refresh address is within the limits specified for

the channel In addition BHE and A0 are both driven

high during refresh bus cycles (this is normally an

invalid bus condition) Data on the AD150 bus is

ignored

A pending refresh request will attempt to abort a

HOLDHLDA bus exchange HLDA is deasserted

when a refresh request is pending and a bus HOLD

is already in progress HOLD must then be released

in order for the M80C186EB to execute the refresh

bus cycle

POWER MANAGEMENT UNIT

The M80C186EB Power Management Unit (PMU) is

provided to control the power consumption of the

device The PMU provides three power modes Ac-

tive Idle and Powerdown

Active

Mode

indicates

that

all

units

the

M80C186EB are functional and the device con-

sumes maximum power (depending on the level of

peripheral operation) Idle Mode freezes the clocks

of the Execution and Bus units at a logic zero state

(all peripherals continue to operate normally) An un-

masked interrupt

NMI

or reset will cause the

M80C186EB to exit the Idle mode

The Powerdown mode freezes all internal clocks at

a logic zero level and disables the crystal oscillator

All internal registers hold their values provided VCC

is maintained Current consumption is reduced to

just transistor junction leakage An NMI or processor

reset will cause the M80C186EB to exit the Power-

down Mode A timing pin is provided to establish the

length of time between exiting Powerdown and re-

suming device operation (Length of time depends

on startup time of crystal oscillator and is application

dependent)

M80C187 Interface

The M80C186EB supports the direct connection of

the M80C187 Numerics Coprocessor

ONCE Test Mode

To facilitate testing and inspection of devices when

fixed into a target system the M80C186EB has a

test mode available which forces all output and in-

putoutput pins to be placed in the high-impedance

state ONCE stands for ‘‘ON Circuit Emulation’’ The

ONCE mode is selected by forcing the A19ONCE

pin LOW (0) during a processor reset (this pin is

weakly held to a HIGH (1) level) while RESIN is ac-

tive

M80C186EB-13 Datasheet(PDF) 13 Page - Intel Corporation

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