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Data Sheet

ADF4106

Rev. E | Page 19 of 24

APPLICATIONS

LOCAL OSCILLATOR FOR LMDS BASE STATION

TRANSMITTER

Figure 22 shows the ADF4106 being used with a VCO to

produce the LO for an LMDS base station.

The reference input signal is applied to the circuit at FREFIN

and, in this case, is terminated in 50 Ω. A typical base station

system would have either a TCXO or an OCXO driving the

reference input without any 50 Ω termination.

To achieve a channel spacing of 1 MHz at the output, the

10 MHz reference input must be divided by 10, using the

on-chip reference divider of the ADF4106.

The charge pump output of the ADF4106 (Pin 2) drives the

loop filter. In calculating the loop filter component values, a

number of items need to be considered. In this example, the

loop filter was designed so that the overall phase margin for

the system would be 45°.

Other PLL system specifications include:

KD = 2.5 mA

KV = 80 MHz/V

Loop Bandwidth = 50 kHz

FPFD = 1 MHz

N = 5800

Extra Reference Spur Attenuation = 10 dB

These specifications are needed and used to derive the loop

filter component values shown in Figure 22.

The circuit in Figure 22 shows a typical phase noise

performance of −83.5 dBc/Hz at 1 kHz offset from the carrier.

Spurs are better than −62 dBc.

The loop filter output drives the VCO, which in turn is fed

back to the RF input of the PLL synthesizer and also drives the

RF output terminal. A T-circuit configuration provides 50 Ω

matching between the VCO output, the RF output, and the RFIN

terminal of the synthesizer.

In a PLL system, it is important to know when the system

is in lock. In Figure 22, this is accomplished by using the

MUXOUT signal from the synthesizer. The MUXOUT pin

can be programmed to monitor various internal signals in the

synthesizer. One of these is the LD or lock-detect signal.

ADF4106

CLK

DATA

1000pF

REFIN

100pF

MUXOUT

100pF

1.5nF

20pF

100pF

Ω

6.2k

Ω

4.3k

Ω

100pF

Ω

NOTE

DECOUPLING CAPACITORS (0.1

µF/10pF) ON AV

DD, DVDD, AND

VP OF THE ADF4106 AND ON VCC OF THE V956ME03 HAVE

BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.

RSET

RFINA

RFINB

AVDD DVDD VP

FREFIN

VDD

LOCK

DETECT

VCC

V956ME03

1, 3, 4, 5, 7, 8,

9, 11, 12, 13

Ω

100pF

RFOUT

5.1k

Ω

Figure 22. Local Oscillator for LMDS Base Station

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