ADV7189B_15 datasheet(39/104 Pages) AD

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ADV7189B

Rev. B | Page 39 of 104

BL_C_VBI Blank Chroma During VBI, Address 0x04[2]

Setting BL_C_VBI high, the Cr and Cb values of all VBI lines

are blanked. This is done so any data that may arrive during

VBI is not decoded as color and output through Cr and Cb.

As a result, it is possible to send VBI lines into the decoder,

then output them through an encoder again, undistorted.

Without this blanking, any wrongly decoded color is encoded

by the video encoder; therefore, the VBI lines are distorted.

Setting BL_C_VBI to 0 decodes and outputs color during VBI.

Setting BL_C_VBI to 1 (default) blanks Cr and Cb values

during VBI.

RANGE Range Selection, Address 0x04[0]

AV codes (as per ITU-R BT-656, formerly known as CCIR-656)

consist of a fixed header made up of 0xFF and 0x00 values.

These two values are reserved and are not to be used for active

video. Additionally, the ITU specifies that the nominal range

for video should be restricted to values between 16 and 235

for luma and 16 to 240 for chroma.

The RANGE bit allows the user to limit the range of values

output by the ADV7189B to the recommended value range.

This bit ensures the reserved values of 255d (0xFF) and 00d

(0x00) are not presented on the output pins unless they are

part of an AV code header.

Table 52. RANGE Function

RANGE

Description

16 ≤ Y ≤ 235

16 ≤ C/P ≤ 240

1 (default)

1 ≤ Y ≤ 254

1 ≤ C/P ≤ 254

AUTO_PDC_EN Automatic Programmed Delay Control,

Address 0x27[6]

Enabling the AUTO_PDC_EN function activates a function

within the ADV7189B that automatically programs the LTA[1:0]

and CTA[2:0] to have the chroma and luma data match delays

for all modes of operation. If set, manual registers LTA[1:0]

and CTA[2:0] are not used by the ADV7189B. If the automatic

mode is disabled (via setting the AUTO_PDC_EN bit to 0), the

values programmed into the LTA[1:0] and CTA[2:0] registers

become active.

When AUTO_PDC_EN is 0, the ADV7189B uses the LTA[1:0]

and CTA[2:0] values for delaying luma and chroma samples.

Refer to the

199H

LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]

and the

200H

CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]

sections.

When AUTO_PDC_EN is 1 (default), the ADV7189B auto-

matically determines the LTA and CTA values to have luma

and chroma aligned at the output.

LTA[1:0] Luma Timing Adjust, Address 0x27[1:0]

The Luma Timing Adjust register allows the user to specify a

timing difference between chroma and luma samples.

Note there is a certain functionality overlap with the CTA[2:0]

•

CVBS input LTA[1:0] = 00

•

YC input LTA[1:0] = 01

•

YPrPb input LTA[1:0] = 01

Table 53. LTA Function

LTA[1:0]

Description

00 (default)

No delay.

Luma 1 CLK (37 ns) delayed.

Luma 2 CLK (74 ns) early.

Luma 1 CLK (37 ns) early.

CTA[2:0] Chroma Timing Adjust, Address 0x27[5:3]

The Chroma timing adjust register allows the user to specify a

timing difference between chroma and luma samples. This can

be used to compensate for external filter group delay differences

in the luma vs. chroma path, and to allow a different number of

pipeline delays while processing the video downstream. Review

this functionality together with the LTA[1:0] register.

The chroma can be delayed/advanced only in chroma pixel

steps. One chroma pixel step is equal to two luma pixels. The

programmable delay occurs after demodulation, where one can

no longer delay by luma pixel steps.

For manual programming, use the following defaults:

•

CVBS input CTA[2:0] = 011.

•

YC input CTA[2:0] = 101.

•

YPrPb input CTA[2:0] = 110.

Table 54. CTA Function

CTA[2:0]

Description

000

Not used.

001

Chroma + 2 chroma pixel (early).

010

Chroma + 1 chroma pixel (early).

011 (default)

No delay.

100

Chroma – 1 chroma pixel (late).

101

Chroma – 2 chroma pixel (late).

110

Chroma – 3 chroma pixel (late).

111

Not used.

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