ADV7189B_15 datasheet(59/104 Pages) AD

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ADV7189B

Rev. B | Page 59 of 104

Interrupt Request Output Operation

When an interrupt event occurs, the interrupt pin INTRQ

goes low with a programmable duration given by

INTRQ_DUR_SEL[1:0].

INTRQ_DURSEL[1:0], Interrupt Duration Select

Address 0x40 (Interrupt Space)[7:6]

Table 76. INTRQ_DUR_SEL

INTRQ_DURSEL[1:0]

Description

00 (default)

3 Xtal periods

15 Xtal periods

63 Xtal periods

Active until cleared

When the active-until-Cleared interrupt duration is selected

and the event that caused the interrupt is no longer in force,

the interrupt persists until it is masked or cleared.

For example, if the ADV7189B loses lock, an interrupt is

generated and the INTRQ pin goes low. If the ADV7189B

returns to the locked state, INTRQ continues to drive low

until the SD_LOCK bit is either masked or cleared.

Interrupt Drive Level

The ADV7189B resets with open drain enabled and all

interrupts masked off. Therefore, INTRQ is in a high

impedance state after reset. 01 or 10 has to be written to

INTRQ_OP_SEL[1:0] for a logic level to be driven out

from the INTRQ pin.

It is also possible to write to a register in the ADV7189B that

manually asserts the INTRQ pin. This bit is MPU_STIM_INTRQ.

INTRQ_OP_SEL[1:0], Interrupt Duration Select

Address 0x40 (Interrupt Space)[1:0]

Table 77. INTRQ_OP_SEL

INTRQ_OP_SEL[1:0]

Description

00 (default)

Open drain

Drive low when active

Drive high when active

Reserved

Multiple Interrupt Events

If Interrupt Event 1 occurs and then Interrupt Event 2 occurs

before the system controller has cleared or masked Interrupt

Event 1, the ADV7189B does not generate a second interrupt

signal. The system controller should check all unmasked

interrupt status bits since more than one can be active.

Macrovision Interrupt Selection Bits

The user can select between pseudo sync pulse and color stripe

detection as follows:

MV_INTRQ_SEL[1:0], Macrovision Interrupt Selection Bits

Address 0x40 (Interrupt Space)[5:4]

Table 78. MV_INTRQ_SEL

MV_INTRQ_SEL[1:0]

Description

Reserved

01 (default)

Pseudo sync only

Color stripe only

Either pseudo sync or color stripe

Additional information relating to the interrupt system is

detailed in

250H

Table 84.

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