AN2871

On-chip voltage regulator (VREG)

Doc ID 15304 Rev 3

13/25

The PLL has the following major features:

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Input clock frequency from an 4 MHz to 40 MHz

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Voltage controlled oscillator (VCO) range from 256 MHz to 512 MHz

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Reduced frequency divider (RFD) for reduced frequency operation without forcing the

PLL to relock

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Frequency-modulated PLL

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Modulation enabled/disabled through software

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Triangle wave modulation

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Programmable modulation depth (±0.25% to ±4% deviation from center frequency)

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Programmable modulation frequency dependent on reference frequency

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Self-clocked mode (SCM) operation

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Input supply same as core supply: 1.2 V

FMPLL supply is shorted with core, without impact on jitter.

At least a couple of 470 pF and 440 nF ceramic capacitors should be placed between the